riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

subsystem: bus wrappers now in BaseSubsystem

Browse Source
This commit is contained in:
Henry Cook
2018-02-20 17:10:16 -08:00
parent b617e26c13
commit 030c6f0206
21 changed files with 119 additions and 156 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/tilelink/BootROM.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.subsystem.{BaseSubsystem, HasResetVectorWire}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
@ -59,7 +59,7 @@ class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], exec
}
/** Adds a boot ROM that contains the DTB describing the system's subsystem. */
trait HasPeripheryBootROM extends HasPeripheryBus {
trait HasPeripheryBootROM { this: BaseSubsystem =>
val dtb: DTB
private val params = p(BootROMParams)
private lazy val contents = {
@ -71,7 +71,7 @@ trait HasPeripheryBootROM extends HasPeripheryBus {
val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
pbus.toVariableWidthSlave(Some("BootROM")){ bootrom.node }
pbus.toVariableWidthSlave(Some("bootrom")){ bootrom.node }
}
/** Subsystem will power-on running at 0x10040 (BootROM) */

1
src/main/scala/devices/tilelink/BusBypass.scala
View File

@ -4,7 +4,6 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._

6
src/main/scala/devices/tilelink/CLINT.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -91,7 +91,7 @@ class CLINT(params: CLINTParams, beatBytes: Int)(implicit p: Parameters) extends
}
/** Trait that will connect a CLINT to a subsystem */
trait HasPeripheryCLINT extends HasPeripheryBus {
trait HasPeripheryCLINT { this: BaseSubsystem =>
val clint = LazyModule(new CLINT(p(CLINTKey), pbus.beatBytes))
pbus.toVariableWidthSlave(Some("CLINT")) { clint.node }
pbus.toVariableWidthSlave(Some("clint")) { clint.node }
}

4
src/main/scala/devices/tilelink/Error.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasSystemBus
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
@ -118,7 +118,7 @@ class DeadlockDevice(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parame
}
}
trait HasSystemErrorSlave extends HasSystemBus {
trait HasSystemErrorSlave { this: BaseSubsystem =>
private val params = p(ErrorParams)
val error = LazyModule(new TLError(params, sbus.beatBytes))
sbus.toSlave(Some("Error")){ error.node }

4
src/main/scala/devices/tilelink/MaskROM.scala
View File

@ -3,9 +3,9 @@
package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.subsystem.{HasPeripheryBus}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
@ -13,7 +13,7 @@ case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width
case object PeripheryMaskROMKey extends Field[Seq[MaskROMParams]]
trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
trait HasPeripheryMaskROMSlave { this: BaseSubsystem =>
val maskROMParams = p(PeripheryMaskROMKey)
val maskROMs = maskROMParams map { params =>
val maskROM = LazyModule(new TLMaskROM(params))

8
src/main/scala/devices/tilelink/Plic.scala
View File

@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -269,8 +269,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
}
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes)))
pbus.toVariableWidthSlave(Some("PLIC")) { plic.node }
trait HasPeripheryPLIC { this: BaseSubsystem =>
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
pbus.toVariableWidthSlave(Some("plic")) { plic.node }
plic.intnode := ibus.toPLIC
}

13
src/main/scala/devices/tilelink/Zero.scala
View File

@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasMemoryBus
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
@ -46,20 +46,17 @@ case class ZeroParams(base: Long, size: Long, beatBytes: Int)
case object ZeroParams extends Field[ZeroParams]
/** Adds a /dev/null slave that generates zero-filled responses to reads */
trait HasMemoryZeroSlave extends HasMemoryBus {
trait HasMemoryZeroSlave { this: BaseSubsystem =>
private val params = p(ZeroParams)
private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
val zeros = memBuses
.map(m => m.toVariableWidthSlave(Some("Zero"))(_))
.zipWithIndex
.map { case (attach, channel) =>
val zeros = memBuses.zipWithIndex.map { case (bus, channel) =>
val channels = memBuses.size
val base = AddressSet(params.base, params.size-1)
val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
val filter = AddressSet(channel * bus.blockBytes, ~((channels-1) * bus.blockBytes))
val address = base.intersect(filter).get
val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
attach { zero.node }
bus.toVariableWidthSlave(Some("Zero")) { zero.node }
zero
}
}