riscv/rocket-chip
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subsystem: bus wrappers now in BaseSubsystem

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This commit is contained in:
Henry Cook
2018-02-20 17:10:16 -08:00
parent b617e26c13
commit 030c6f0206
21 changed files with 119 additions and 156 deletions
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9
src/main/scala/devices/debug/Periphery.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug
import Chisel._
import chisel3.core.{IntParam, Input, Output}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.jtag._
@ -26,12 +26,9 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), based on a global parameter.
*/
trait HasPeripheryDebug extends HasPeripheryBus {
val module: HasPeripheryDebugModuleImp
trait HasPeripheryDebug { this: BaseSubsystem =>
val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
pbus.toVariableWidthSlave(Some("Debug")){ debug.node }
pbus.toVariableWidthSlave(Some("debug")){ debug.node }
}
trait HasPeripheryDebugBundle {