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Support a degenerate PLIC with no interrupts

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Resolves #249
This commit is contained in:
Andrew Waterman 2016-09-07 11:20:21 -07:00
parent 92718e4b61
commit 02a2439222
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/devices/Plic.scala
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@ -51,7 +51,7 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
def claimOffset = 4 def claimOffset = 4
def priorityBytes = 4 def priorityBytes = 4
require(nDevices > 0 && nDevices <= maxDevices) require(nDevices <= maxDevices)
require(nHarts > 0 && nHarts <= maxHarts) require(nHarts > 0 && nHarts <= maxHarts)
require(nPriorities >= 0 && nPriorities <= nDevices) require(nPriorities >= 0 && nPriorities <= nDevices)
} }
@ -117,7 +117,7 @@ class PLIC(val cfg: PLICConfig)(implicit val p: Parameters) extends Module
val rdata = Wire(init = UInt(0, tlDataBits)) val rdata = Wire(init = UInt(0, tlDataBits))
val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask()) val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
when (addr >= cfg.hartBase) { if (cfg.nDevices > 0) when (addr >= cfg.hartBase) {
val word = val word =
if (tlDataBytes > cfg.claimOffset) UInt(0) if (tlDataBytes > cfg.claimOffset) UInt(0)
else addr(log2Up(cfg.claimOffset),log2Up(tlDataBytes)) else addr(log2Up(cfg.claimOffset),log2Up(tlDataBytes))