amo_shift_bits -> amo_shift_bytes
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@ -79,6 +79,7 @@ trait HasTileLinkParameters {
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val tlNetworkPreservesPointToPointOrdering = false
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val tlNetworkDoesNotInterleaveBeats = true
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val amoAluOperandBits = p(AmoAluOperandBits)
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val amoAluOperandBytes = amoAluOperandBits/8
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}
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abstract class TLModule(implicit val p: Parameters) extends Module
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@ -162,9 +163,9 @@ trait HasAcquireUnion extends HasTileLinkParameters {
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def op_size(dummy: Int = 0) = union(addrByteOff-1, opSizeOff)
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/** Byte address for [[uncore.PutAtomic]] operand */
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def addr_byte(dummy: Int = 0) = union(addrByteMSB-1, addrByteOff)
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def amo_offset(dummy: Int = 0) = addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBits/8))
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def amo_offset(dummy: Int = 0) = addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBytes))
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/** Bit offset of [[uncore.PutAtomic]] operand */
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def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset()
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def amo_shift_bytes(dummy: Int = 0) = UInt(amoAluOperandBytes)*amo_offset()
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/** Write mask for [[uncore.Put]], [[uncore.PutBlock]], [[uncore.PutAtomic]] */
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def wmask(dummy: Int = 0): UInt = {
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Mux(isBuiltInType(Acquire.putAtomicType),
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