riscv/rocket-chip
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Rename trace.addr -> iaddr

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This commit is contained in:
Andrew Waterman 2017-09-20 14:32:41 -07:00
parent 1cb91eed41
commit 026fa14bf8
2 changed files with 7 additions and 7 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -151,7 +151,7 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val addr = UInt(width = coreMaxAddrBits)
val iaddr = UInt(width = coreMaxAddrBits)
val insn = UInt(width = iLen)
val priv = UInt(width = 3)
val exception = Bool()
@ -771,7 +771,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
t.exception := io.retire >= i && exception
t.valid := io.retire > i || t.exception
t.insn := insn
t.addr := io.pc
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0))
t.tval := badaddr_value

10
src/main/scala/rocket/RocketCore.scala
View File

@ -675,16 +675,16 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
when (t.valid) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd+UInt(32))
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+UInt(32))
}
.elsewhen (wxd && rd =/= UInt(0) && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.addr, t.insn, rd, rf_wdata)
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= UInt(0) && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd)
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.addr, t.insn)
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
@ -694,7 +694,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
}
else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).addr(vaddrBitsExtended-1, 0),
io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0),
Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),