riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Rename trace.addr -> iaddr

Browse Source
This commit is contained in:
Andrew Waterman
2017-09-20 14:32:41 -07:00
parent 1cb91eed41
commit 026fa14bf8
2 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/CSR.scala
View File

@ -151,7 +151,7 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val addr = UInt(width = coreMaxAddrBits)
val iaddr = UInt(width = coreMaxAddrBits)
val insn = UInt(width = iLen)
val priv = UInt(width = 3)
val exception = Bool()
@ -771,7 +771,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
t.exception := io.retire >= i && exception
t.valid := io.retire > i || t.exception
t.insn := insn
t.addr := io.pc
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0))
t.tval := badaddr_value