From 0268959c24364ecc1ed66b73fad2e3ce19993e36 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Wed, 27 Sep 2017 12:02:04 -0700
Subject: [PATCH] rocket: move interrupt synchronizers to correct side of
 crossing

---
 src/main/scala/coreplex/RocketCoreplex.scala | 6 +++++-
 src/main/scala/tile/RocketTile.scala         | 6 ------
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala
index 04689407..766aee01 100644
--- a/src/main/scala/coreplex/RocketCoreplex.scala
+++ b/src/main/scala/coreplex/RocketCoreplex.scala
@@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus
     lip.foreach { coreIntXbar.intnode := _ }                // lip
     wrapper.coreIntNode   := coreIntXbar.intnode
 
-    wrapper.intOutputNode.foreach { plic.intnode := _ }
+    wrapper.intOutputNode.foreach { case int =>
+      val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
+      rocketIntXing.intnode := int
+      plic.intnode := rocketIntXing.intnode
+    }
 
     wrapper
   }
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 8f5ca043..b9aaa542 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -211,12 +211,6 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
   def outputInterruptXingLatency: Int
 
-  rocket.intOutputNode.foreach { rocketIntOutputNode =>
-    val outXing = LazyModule(new IntXing(outputInterruptXingLatency))
-    intOutputNode.get := outXing.intnode
-    outXing.intnode := rocketIntOutputNode
-  }
-
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new CoreBundle
         with HasExternallyDrivenTileConstants