diff --git a/src/main/scala/amba/axi4/SRAM.scala b/src/main/scala/amba/axi4/SRAM.scala
index 38686f7e..72e580c1 100644
--- a/src/main/scala/amba/axi4/SRAM.scala
+++ b/src/main/scala/amba/axi4/SRAM.scala
@@ -37,21 +37,26 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
 
     val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
     val w_addr = Cat((mask zip (in.aw.bits.addr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
+    val r_sel0 = address.contains(in.ar.bits.addr)
+    val w_sel0 = address.contains(in.aw.bits.addr)
 
     val w_full = RegInit(Bool(false))
     val w_id   = Reg(UInt())
     val w_user = Reg(UInt(width = 1 max in.params.userBits))
+    val r_sel1 = Reg(r_sel0)
+    val w_sel1 = Reg(w_sel0)
 
     when (in. b.fire()) { w_full := Bool(false) }
     when (in.aw.fire()) { w_full := Bool(true) }
 
     when (in.aw.fire()) {
       w_id := in.aw.bits.id
+      w_sel1 := w_sel0
       in.aw.bits.user.foreach { w_user := _ }
     }
 
     val wdata = Vec.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
-    when (in.aw.fire()) {
+    when (in.aw.fire() && w_sel0) {
       mem.write(w_addr, wdata, in.w.bits.strb.toBools)
     }
 
@@ -60,7 +65,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
     in. w.ready := in.aw.valid && (in.b.ready || !w_full)
 
     in.b.bits.id   := w_id
-    in.b.bits.resp := AXI4Parameters.RESP_OKAY
+    in.b.bits.resp := Mux(w_sel1, AXI4Parameters.RESP_OKAY, AXI4Parameters.RESP_DECERR)
     in.b.bits.user.foreach { _ := w_user }
 
     val r_full = RegInit(Bool(false))
@@ -72,6 +77,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
 
     when (in.ar.fire()) {
       r_id := in.ar.bits.id
+      r_sel1 := r_sel0
       in.ar.bits.user.foreach { r_user := _ }
     }
 
@@ -82,7 +88,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
     in.ar.ready := in.r.ready || !r_full
 
     in.r.bits.id   := r_id
-    in.r.bits.resp := AXI4Parameters.RESP_OKAY
+    in.r.bits.resp := Mux(r_sel1, AXI4Parameters.RESP_OKAY, AXI4Parameters.RESP_DECERR)
     in.r.bits.data := Cat(rdata.reverse)
     in.r.bits.user.foreach { _ := r_user }
     in.r.bits.last := Bool(true)