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tilelink2: switch to DecoupledIO syntax

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This commit is contained in:
Wesley W. Terpstra 2016-10-12 18:09:01 -07:00
parent 980bb3fbfd
commit 023c6402e9
6 changed files with 34 additions and 38 deletions
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3
src/main/scala/uncore/tilelink2/Arbiter.scala
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@ -3,7 +3,6 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.IrrevocableIO
import diplomacy._ import diplomacy._
object TLArbiter object TLArbiter
@ -14,7 +13,7 @@ object TLArbiter
val lowestIndexFirst: Policy = (valids, idle) => val lowestIndexFirst: Policy = (valids, idle) =>
valids.scanLeft(Bool(true))(_ && !_).init valids.scanLeft(Bool(true))(_ && !_).init
def apply[T <: Data](policy: Policy)(sink: IrrevocableIO[T], sources: (UInt, IrrevocableIO[T])*) { def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*) {
if (sources.isEmpty) { if (sources.isEmpty) {
sink.valid := Bool(false) sink.valid := Bool(false)
} else { } else {

46
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -3,7 +3,7 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.{Irrevocable, IrrevocableIO, ReadyValidIO} import chisel3.util.{ReadyValidIO}
import diplomacy._ import diplomacy._
import util.{AsyncQueueSource, AsyncQueueSink, GenericParameterizedBundle} import util.{AsyncQueueSource, AsyncQueueSink, GenericParameterizedBundle}
@ -165,11 +165,11 @@ final class TLBundleE(params: TLBundleParameters)
class TLBundle(params: TLBundleParameters) extends TLBundleBase(params) class TLBundle(params: TLBundleParameters) extends TLBundleBase(params)
{ {
val a = Irrevocable(new TLBundleA(params)) val a = Decoupled(new TLBundleA(params))
val b = Irrevocable(new TLBundleB(params)).flip val b = Decoupled(new TLBundleB(params)).flip
val c = Irrevocable(new TLBundleC(params)) val c = Decoupled(new TLBundleC(params))
val d = Irrevocable(new TLBundleD(params)).flip val d = Decoupled(new TLBundleD(params)).flip
val e = Irrevocable(new TLBundleE(params)) val e = Decoupled(new TLBundleE(params))
} }
object TLBundle object TLBundle
@ -177,20 +177,20 @@ object TLBundle
def apply(params: TLBundleParameters) = new TLBundle(params) def apply(params: TLBundleParameters) = new TLBundle(params)
} }
final class IrrevocableSnoop[+T <: Data](gen: T) extends Bundle final class DecoupledSnoop[+T <: Data](gen: T) extends Bundle
{ {
val ready = Bool() val ready = Bool()
val valid = Bool() val valid = Bool()
val bits = gen.asOutput val bits = gen.asOutput
def fire(dummy: Int = 0) = ready && valid def fire(dummy: Int = 0) = ready && valid
override def cloneType: this.type = new IrrevocableSnoop(gen).asInstanceOf[this.type] override def cloneType: this.type = new DecoupledSnoop(gen).asInstanceOf[this.type]
} }
object IrrevocableSnoop object DecoupledSnoop
{ {
def apply[T <: Data](i: IrrevocableIO[T]) = { def apply[T <: Data](i: DecoupledIO[T]) = {
val out = Wire(new IrrevocableSnoop(i.bits)) val out = Wire(new DecoupledSnoop(i.bits))
out.ready := i.ready out.ready := i.ready
out.valid := i.valid out.valid := i.valid
out.bits := i.bits out.bits := i.bits
@ -200,22 +200,22 @@ object IrrevocableSnoop
class TLBundleSnoop(params: TLBundleParameters) extends TLBundleBase(params) class TLBundleSnoop(params: TLBundleParameters) extends TLBundleBase(params)
{ {
val a = new IrrevocableSnoop(new TLBundleA(params)) val a = new DecoupledSnoop(new TLBundleA(params))
val b = new IrrevocableSnoop(new TLBundleB(params)) val b = new DecoupledSnoop(new TLBundleB(params))
val c = new IrrevocableSnoop(new TLBundleC(params)) val c = new DecoupledSnoop(new TLBundleC(params))
val d = new IrrevocableSnoop(new TLBundleD(params)) val d = new DecoupledSnoop(new TLBundleD(params))
val e = new IrrevocableSnoop(new TLBundleE(params)) val e = new DecoupledSnoop(new TLBundleE(params))
} }
object TLBundleSnoop object TLBundleSnoop
{ {
def apply(x: TLBundle) = { def apply(x: TLBundle) = {
val out = Wire(new TLBundleSnoop(x.params)) val out = Wire(new TLBundleSnoop(x.params))
out.a <> IrrevocableSnoop(x.a) out.a <> DecoupledSnoop(x.a)
out.b <> IrrevocableSnoop(x.b) out.b <> DecoupledSnoop(x.b)
out.c <> IrrevocableSnoop(x.c) out.c <> DecoupledSnoop(x.c)
out.d <> IrrevocableSnoop(x.d) out.d <> DecoupledSnoop(x.d)
out.e <> IrrevocableSnoop(x.e) out.e <> DecoupledSnoop(x.e)
out out
} }
} }
@ -234,14 +234,14 @@ final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle
object FromAsyncBundle object FromAsyncBundle
{ {
def apply[T <: Data](x: AsyncBundle[T], sync: Int = 3): IrrevocableIO[T] = { def apply[T <: Data](x: AsyncBundle[T], sync: Int = 3): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(x.mem(0), x.depth, sync)) val sink = Module(new AsyncQueueSink(x.mem(0), x.depth, sync))
x.ridx := sink.io.ridx x.ridx := sink.io.ridx
sink.io.widx := x.widx sink.io.widx := x.widx
sink.io.mem := x.mem sink.io.mem := x.mem
sink.io.source_reset_n := x.source_reset_n sink.io.source_reset_n := x.source_reset_n
x.sink_reset_n := !sink.reset x.sink_reset_n := !sink.reset
val out = Wire(Irrevocable(x.mem(0))) val out = Wire(Decoupled(x.mem(0)))
out.valid := sink.io.deq.valid out.valid := sink.io.deq.valid
out.bits := sink.io.deq.bits out.bits := sink.io.deq.bits
sink.io.deq.ready := out.ready sink.io.deq.ready := out.ready

3
src/main/scala/uncore/tilelink2/Edges.scala
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@ -4,7 +4,6 @@ package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO
import diplomacy._ import diplomacy._
class TLEdge( class TLEdge(
@ -232,7 +231,7 @@ class TLEdge(
(first, last, beats1 & ~counter1) (first, last, beats1 & ~counter1)
} }
def firstlast(x: IrrevocableIO[TLChannel]): (Bool, Bool, UInt) = firstlast(x.bits, x.fire()) def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, UInt) = firstlast(x.bits, x.fire())
} }
class TLEdgeOut( class TLEdgeOut(

10
src/main/scala/uncore/tilelink2/Monitor.scala
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@ -281,7 +281,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} }
def legalizeMultibeatA(a: IrrevocableSnoop[TLBundleA], edge: TLEdge)(implicit sourceInfo: SourceInfo) { def legalizeMultibeatA(a: DecoupledSnoop[TLBundleA], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
val (a_first, _, _) = edge.firstlast(a.bits, a.fire()) val (a_first, _, _) = edge.firstlast(a.bits, a.fire())
val opcode = Reg(UInt()) val opcode = Reg(UInt())
val param = Reg(UInt()) val param = Reg(UInt())
@ -304,7 +304,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
} }
} }
def legalizeMultibeatB(b: IrrevocableSnoop[TLBundleB], edge: TLEdge)(implicit sourceInfo: SourceInfo) { def legalizeMultibeatB(b: DecoupledSnoop[TLBundleB], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
val (b_first, _, _) = edge.firstlast(b.bits, b.fire()) val (b_first, _, _) = edge.firstlast(b.bits, b.fire())
val opcode = Reg(UInt()) val opcode = Reg(UInt())
val param = Reg(UInt()) val param = Reg(UInt())
@ -327,7 +327,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
} }
} }
def legalizeMultibeatC(c: IrrevocableSnoop[TLBundleC], edge: TLEdge)(implicit sourceInfo: SourceInfo) { def legalizeMultibeatC(c: DecoupledSnoop[TLBundleC], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
val (c_first, _, _) = edge.firstlast(c.bits, c.fire()) val (c_first, _, _) = edge.firstlast(c.bits, c.fire())
val opcode = Reg(UInt()) val opcode = Reg(UInt())
val param = Reg(UInt()) val param = Reg(UInt())
@ -353,7 +353,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
} }
} }
def legalizeMultibeatD(d: IrrevocableSnoop[TLBundleD], edge: TLEdge)(implicit sourceInfo: SourceInfo) { def legalizeMultibeatD(d: DecoupledSnoop[TLBundleD], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
val (d_first, _, _) = edge.firstlast(d.bits, d.fire()) val (d_first, _, _) = edge.firstlast(d.bits, d.fire())
val opcode = Reg(UInt()) val opcode = Reg(UInt())
val param = Reg(UInt()) val param = Reg(UInt())
@ -386,7 +386,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
legalizeMultibeatD(bundle.d, edge) legalizeMultibeatD(bundle.d, edge)
} }
def legalizeIrrevocable(irr: IrrevocableSnoop[TLChannel], edge: TLEdge)(implicit sourceInfo: SourceInfo) { def legalizeIrrevocable(irr: DecoupledSnoop[TLChannel], edge: TLEdge)(implicit sourceInfo: SourceInfo) {
val last_v = RegNext(irr.valid, Bool(false)) val last_v = RegNext(irr.valid, Bool(false))
val last_r = RegNext(irr.ready, Bool(false)) val last_r = RegNext(irr.ready, Bool(false))
val last_b = RegNext(irr.bits) val last_b = RegNext(irr.bits)

7
src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -4,7 +4,6 @@ package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.{Irrevocable, IrrevocableIO}
import diplomacy._ import diplomacy._
import scala.math.{min,max} import scala.math.{min,max}
@ -22,7 +21,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
val out = node.bundleOut val out = node.bundleOut
} }
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: IrrevocableIO[T], edgeOut: TLEdge, out: IrrevocableIO[T]) = { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes val ratio = outBytes / inBytes
@ -86,7 +85,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
} }
} }
def split[T <: TLDataChannel](edgeIn: TLEdge, in: IrrevocableIO[T], edgeOut: TLEdge, out: IrrevocableIO[T]) = { def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes val ratio = inBytes / outBytes
@ -136,7 +135,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
// addr_lo gets truncated automagically // addr_lo gets truncated automagically
} }
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: IrrevocableIO[T], edgeOut: TLEdge, out: IrrevocableIO[T]) = { def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through // nothing to do; pass it through
out <> in out <> in

3
src/main/scala/uncore/tilelink2/Xbar.scala
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@ -3,7 +3,6 @@
package uncore.tilelink2 package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.util.IrrevocableIO
import diplomacy._ import diplomacy._
class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule
@ -141,7 +140,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends Lazy
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Replicate an input port to each output port // Replicate an input port to each output port
def fanout[T <: TLChannel](input: IrrevocableIO[T], select: Seq[Bool]) = { def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool]) = {
val filtered = Wire(Vec(select.size, input)) val filtered = Wire(Vec(select.size, input))
for (i <- 0 until select.size) { for (i <- 0 until select.size) {
filtered(i).bits := input.bits filtered(i).bits := input.bits