riscv/rocket-chip
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diplomacy: make config.Parameters available in bundle connect()

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This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
This commit is contained in:
Wesley W. Terpstra committed 2016-12-07 12:24:01 -08:00
1 parent 915697cb09
commit 020fbe8be9
48 files changed
+184 -153
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src/main/scala/uncore/tilelink2/SRAM.scala
+4 -3
View File
@@ -3,9 +3,10 @@
package uncore.tilelink2
import Chisel._
import config._
import diplomacy._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
{
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
@@ -84,7 +85,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
/** Synthesizeable unit testing */
import unittest._
class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel)
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
@@ -97,6 +98,6 @@ class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
}
}
class TLRAMSimpleTest(ramBeatBytes: Int) extends UnitTest(timeout = 500000) {
class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
}