diplomacy: make config.Parameters available in bundle connect()

This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.

src/main/scala/uncore/devices/Debug.scala

@@ -332,8 +332,7 @@ object ToAsyncDebugBus
 }
 
 trait HasDebugModuleParameters {
-  val params : Parameters
-  implicit val p = params
+  implicit val p: Parameters
   val cfg = p(DMKey)
 }
 
@@ -850,8 +849,8 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
 
 class TLDebugModule(address: BigInt = 0)(implicit p: Parameters)
   extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8, executable=true)(
-  new TLRegBundle(p, _ )    with DebugModuleBundle)(
-  new TLRegModule(p, _, _)  with DebugModule)
+  new TLRegBundle((), _ )    with DebugModuleBundle)(
+  new TLRegModule((), _, _)  with DebugModule)
 
 
 /** Synchronizers for DebugBus

src/main/scala/uncore/devices/Plic.scala

@@ -52,7 +52,7 @@ object PLICConsts
 }
 
 /** Platform-Level Interrupt Controller */
-class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit val p: Parameters) extends LazyModule
+class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
 {
   val contextsPerHart = if (supervisor) 2 else 1
   require (maxPriorities >= 0)

src/main/scala/uncore/devices/Prci.scala

@@ -32,8 +32,7 @@ object ClintConsts
 }
 
 trait MixCoreplexLocalInterrupterParameters {
-  val params: Parameters
-  implicit val p = params
+  implicit val p: Parameters
 }
 
 trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
@@ -83,10 +82,10 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
 
 /** Power, Reset, Clock, Interrupt */
 // Magic TL2 Incantation to create a TL2 Slave
-class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters)
+class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters)
   extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
-  new TLRegBundle(p, _)    with CoreplexLocalInterrupterBundle)(
-  new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
+  new TLRegBundle((), _)    with CoreplexLocalInterrupterBundle)(
+  new TLRegModule((), _, _) with CoreplexLocalInterrupterModule)
 {
   val globalConfigString = Seq(
     s"rtc {\n",

src/main/scala/uncore/devices/Rom.scala

@@ -12,7 +12,7 @@ import uncore.tilelink2._
 import uncore.util._
 import config._
 
-class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
+class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
 {
   val node = TLManagerNode(beatBytes, TLManagerParameters(
     address     = List(AddressSet(base, size-1)),