riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: make config.Parameters available in bundle connect()

Browse Source 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
This commit is contained in:
Wesley W. Terpstra
2016-12-01 17:46:52 -08:00
parent 915697cb09
commit 020fbe8be9
48 changed files with 184 additions and 153 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/main/scala/uncore/axi4/Buffer.scala
View File

@ -4,11 +4,12 @@ package uncore.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import scala.math.max
// pipe is only used if a queue has depth = 1
class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true) extends LazyModule
class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require (aw >= 0)
require (w >= 0)
@ -37,12 +38,12 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
object AXI4Buffer
{
// applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
def apply() (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x)
def apply(entries: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x)
def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x)
def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x)
def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x)
def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x)
def apply(entries: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x)
def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x)
def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x)
def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x)
def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r, pipe))
buffer.node := x
buffer.node

5
src/main/scala/uncore/axi4/Fragmenter.scala
View File

@ -5,12 +5,13 @@ package uncore.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO
import config._
import diplomacy._
import scala.math.{min,max}
import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH}
// lite: masters all use only one ID => reads will not be interleaved
class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true) extends LazyModule
class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val maxBeats = 1 << AXI4Parameters.lenBits
def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) =
@ -287,7 +288,7 @@ class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Mo
object AXI4Fragmenter
{
// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational))
fragmenter.node := x
fragmenter.node

3
src/main/scala/uncore/axi4/Nodes.scala
View File

@ -4,6 +4,7 @@ package uncore.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
@ -23,7 +24,7 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString
override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString
def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => { bi <> bo })
}

1
src/main/scala/uncore/axi4/Parameters.scala
View File

@ -3,6 +3,7 @@
package uncore.axi4
import Chisel._
import config._
import diplomacy._
import scala.math.max

8
src/main/scala/uncore/axi4/RegisterRouter.scala
View File

@ -3,6 +3,7 @@
package uncore.axi4
import Chisel._
import config._
import diplomacy._
import regmapper._
import scala.math.{min,max}
@ -77,16 +78,17 @@ object AXI4RegisterNode
// These convenience methods below combine to make it possible to create a AXI4
// register mapped device from a totally abstract register mapped device.
abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule
abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
{
val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
}
case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])
case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters)
class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
{
implicit val p = arg.p
val interrupts = arg.interrupts
val in = arg.in
}
@ -104,7 +106,7 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: =>
class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp]
(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
(bundleBuilder: AXI4RegBundleArg => B)
(moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)
(moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)(implicit p: Parameters)
extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
{
require (isPow2(size))

3
src/main/scala/uncore/axi4/SRAM.scala
View File

@ -3,9 +3,10 @@
package uncore.axi4
import Chisel._
import config._
import diplomacy._
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
{
val node = AXI4SlaveNode(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters(

21
src/main/scala/uncore/axi4/Test.scala
View File

@ -3,19 +3,20 @@
package uncore.axi4
import Chisel._
import config._
import diplomacy._
import uncore.tilelink2._
import unittest._
class RRTest0(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
class RRTest0(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
new AXI4RegBundle((), _) with RRTest0Bundle)(
new AXI4RegModule((), _, _) with RRTest0Module)
class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
new AXI4RegBundle((), _) with RRTest1Bundle)(
new AXI4RegModule((), _, _) with RRTest1Module)
class AXI4LiteFuzzRAM extends LazyModule
class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
{
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
@ -33,12 +34,12 @@ class AXI4LiteFuzzRAM extends LazyModule
}
}
class AXI4LiteFuzzRAMTest extends UnitTest(500000) {
class AXI4LiteFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
io.finished := dut.io.finished
}
class AXI4FullFuzzRAM extends LazyModule
class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
{
val fuzz = LazyModule(new TLFuzzer(5000))
val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
@ -56,12 +57,12 @@ class AXI4FullFuzzRAM extends LazyModule
}
}
class AXI4FullFuzzRAMTest extends UnitTest(500000) {
class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
io.finished := dut.io.finished
}
class AXI4FuzzMaster extends LazyModule
class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
{
val node = AXI4OutputNode()
val fuzz = LazyModule(new TLFuzzer(5000))
@ -80,7 +81,7 @@ class AXI4FuzzMaster extends LazyModule
}
}
class AXI4FuzzSlave extends LazyModule
class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
{
val node = AXI4InputNode()
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
@ -94,7 +95,7 @@ class AXI4FuzzSlave extends LazyModule
}
}
class AXI4FuzzBridge extends LazyModule
class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
{
val master = LazyModule(new AXI4FuzzMaster)
val slave = LazyModule(new AXI4FuzzSlave)
@ -106,7 +107,7 @@ class AXI4FuzzBridge extends LazyModule
}
}
class AXI4BridgeTest extends UnitTest(500000) {
class AXI4BridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
val dut = Module(LazyModule(new AXI4FuzzBridge).module)
io.finished := dut.io.finished
}

5
src/main/scala/uncore/axi4/ToTL.scala
View File

@ -4,6 +4,7 @@ package uncore.axi4
import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import uncore.tilelink2._
@ -30,7 +31,7 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
numPO = 1 to 1,
numPI = 1 to 1)
class AXI4ToTL extends LazyModule
class AXI4ToTL()(implicit p: Parameters) extends LazyModule
{
val node = AXI4ToTLNode()
@ -176,7 +177,7 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
object AXI4ToTL
{
def apply()(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val tl = LazyModule(new AXI4ToTL)
tl.node := x
tl.node