riscv/rocket-chip
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diplomacy: make config.Parameters available in bundle connect()

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This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
This commit is contained in:
Wesley W. Terpstra
2016-12-01 17:46:52 -08:00
parent 915697cb09
commit 020fbe8be9
48 changed files with 184 additions and 153 deletions
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2
src/main/scala/rocket/Dcache.scala
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@ -42,7 +42,7 @@ class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit
override lazy val module = new DCacheModule(this)
}
class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) {
class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val maxUncachedInFlight = cfg.nMMIOs

4
src/main/scala/rocket/HellaCache.scala
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@ -129,7 +129,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
val ordered = Bool(INPUT)
}
abstract class HellaCache(val cfg: DCacheConfig)(implicit val p: Parameters) extends LazyModule {
abstract class HellaCache(val cfg: DCacheConfig)(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(TLClientParameters(
sourceId = IdRange(0, cfg.nMSHRs + cfg.nMMIOs),
supportsProbe = TransferSizes(p(CacheBlockBytes))))
@ -142,7 +142,7 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle
val mem = outer.node.bundleOut
}
class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends LazyModuleImp(outer)
class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
with HasL1HellaCacheParameters {
implicit val cfg = outer.cfg
val io = new HellaCacheBundle(outer)

2
src/main/scala/rocket/NBDcache.scala
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@ -675,7 +675,7 @@ class NonBlockingDCache(cfg: DCacheConfig)(implicit p: Parameters) extends Hella
override lazy val module = new NonBlockingDCacheModule(this)
}
class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) {
class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule(outer) {
require(isPow2(nWays)) // TODO: relax this
require(p(DataScratchpadSize) == 0)

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -11,7 +11,7 @@ import uncore.constants._
import uncore.tilelink2._
import uncore.util._
class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule {
class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
val coreDataBytes = p(XLen)/8
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(