Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/tilelink/Bus.scala

@@ -0,0 +1,96 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.tilelink
+
+import Chisel._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+/** Specifies widths of various attachement points in the SoC */
+trait TLBusParams {
+  val beatBytes: Int
+  val blockBytes: Int
+  val masterBuffering: BufferParams
+  val slaveBuffering: BufferParams
+
+  def beatBits: Int = beatBytes * 8
+  def blockBits: Int = blockBytes * 8
+  def blockBeats: Int = blockBytes / beatBytes
+  def blockOffset: Int = log2Up(blockBytes)
+}
+
+abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends TLBusParams {
+  val beatBytes = params.beatBytes
+  val blockBytes = params.blockBytes
+  val masterBuffering = params.masterBuffering
+  val slaveBuffering = params.slaveBuffering
+  require(blockBytes % beatBytes == 0)
+
+  private val xbar = LazyModule(new TLXbar)
+  private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
+  private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
+  private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
+  private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
+
+  xbar.node :=* master_buffer.node
+  slave_buffer.node :*= xbar.node
+  slave_frag.node :*= slave_buffer.node
+  slave_ww.node :*= slave_buffer.node
+
+  protected def outwardNode: TLOutwardNode = xbar.node
+  protected def outwardBufNode: TLOutwardNode = slave_buffer.node
+  protected def outwardFragNode: TLOutwardNode = slave_frag.node
+  protected def outwardWWNode: TLOutwardNode = slave_ww.node
+  protected def inwardNode: TLInwardNode = xbar.node
+  protected def inwardBufNode: TLInwardNode = master_buffer.node
+
+  def edgesIn = xbar.node.edgesIn
+
+  def bufferFromMasters: TLInwardNode = inwardBufNode
+
+  def bufferToSlaves: TLOutwardNode = outwardBufNode 
+
+  def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node :*= outwardNode
+    source.node
+  }
+
+  def toRationalSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardNode
+    source.node
+  }
+
+  def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
+
+  def toAsyncVariableWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node :*= outwardFragNode
+    source.node
+  }
+
+  def toRationalVariableWidthSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardFragNode
+    source.node
+  }
+
+  def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
+
+  def toAsyncFixedWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node := outwardWWNode
+    source.node
+  }
+
+  def toRationalFixedWidthSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardWWNode
+    source.node
+  }
+
+  def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
+
+}