Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/tilelink/AtomicAutomata.scala

@@ -22,7 +22,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
       def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
       val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
       // Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
-      require (!m.supportsPutFull || !m.supportsGet || canDoit)
+      require (!m.supportsPutFull || !m.supportsGet || canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})")
       m.copy(
         supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
         supportsLogical    = if (!logical    || !canDoit) m.supportsLogical    else widen(m.supportsLogical))

src/main/scala/tilelink/Broadcast.scala

@@ -29,8 +29,8 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
           if (m.regionType == RegionType.UNCACHED) {
             // The device had better support line transfers
             val lowerBound = max(m.supportsPutFull.min, m.supportsGet.min)
-            require (!m.supportsPutFull || m.supportsPutFull.contains(lineBytes))
-            require (!m.supportsGet     || m.supportsGet    .contains(lineBytes))
+            require (!m.supportsPutFull || m.supportsPutFull.contains(lineBytes), s"${m.name} only supports PutFull(${m.supportsPutFull}), which does not include $lineBytes")
+            require (!m.supportsGet     || m.supportsGet    .contains(lineBytes), s"${m.name} only supports Get(${m.supportsGet}), which does not include $lineBytes")
             m.copy(
               regionType         = RegionType.TRACKED,
               supportsAcquireB   = TransferSizes(lowerBound, lineBytes),

src/main/scala/tilelink/Bus.scala

@@ -0,0 +1,96 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.tilelink
+
+import Chisel._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+/** Specifies widths of various attachement points in the SoC */
+trait TLBusParams {
+  val beatBytes: Int
+  val blockBytes: Int
+  val masterBuffering: BufferParams
+  val slaveBuffering: BufferParams
+
+  def beatBits: Int = beatBytes * 8
+  def blockBits: Int = blockBytes * 8
+  def blockBeats: Int = blockBytes / beatBytes
+  def blockOffset: Int = log2Up(blockBytes)
+}
+
+abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends TLBusParams {
+  val beatBytes = params.beatBytes
+  val blockBytes = params.blockBytes
+  val masterBuffering = params.masterBuffering
+  val slaveBuffering = params.slaveBuffering
+  require(blockBytes % beatBytes == 0)
+
+  private val xbar = LazyModule(new TLXbar)
+  private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
+  private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
+  private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
+  private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
+
+  xbar.node :=* master_buffer.node
+  slave_buffer.node :*= xbar.node
+  slave_frag.node :*= slave_buffer.node
+  slave_ww.node :*= slave_buffer.node
+
+  protected def outwardNode: TLOutwardNode = xbar.node
+  protected def outwardBufNode: TLOutwardNode = slave_buffer.node
+  protected def outwardFragNode: TLOutwardNode = slave_frag.node
+  protected def outwardWWNode: TLOutwardNode = slave_ww.node
+  protected def inwardNode: TLInwardNode = xbar.node
+  protected def inwardBufNode: TLInwardNode = master_buffer.node
+
+  def edgesIn = xbar.node.edgesIn
+
+  def bufferFromMasters: TLInwardNode = inwardBufNode
+
+  def bufferToSlaves: TLOutwardNode = outwardBufNode 
+
+  def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node :*= outwardNode
+    source.node
+  }
+
+  def toRationalSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardNode
+    source.node
+  }
+
+  def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
+
+  def toAsyncVariableWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node :*= outwardFragNode
+    source.node
+  }
+
+  def toRationalVariableWidthSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardFragNode
+    source.node
+  }
+
+  def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
+
+  def toAsyncFixedWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
+    val source = LazyModule(new TLAsyncCrossingSource(sync))
+    source.node := outwardWWNode
+    source.node
+  }
+
+  def toRationalFixedWidthSlaves: TLRationalOutwardNode = {
+    val source = LazyModule(new TLRationalCrossingSource())
+    source.node :*= outwardWWNode
+    source.node
+  }
+
+  def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
+
+}

src/main/scala/tilelink/Parameters.scala

@@ -76,7 +76,9 @@ case class TLManagerPortParameters(
   require (endSinkId >= 0)
   require (minLatency >= 0)
 
-  def requireFifo() = managers.foreach { m =>require (m.fifoId == Some(0))  }
+  def requireFifo() = managers.foreach { m =>
+    require(m.fifoId == Some(0), s"${m.name} had fifoId ${m.fifoId}, which was not 0 (${managers.map(s => (s.name, s.fifoId))}) ")
+  }
 
   // Bounds on required sizes
   def maxAddress  = managers.map(_.maxAddress).max
@@ -315,7 +317,7 @@ case class TLEdgeParameters(
   val maxLgSize = log2Ceil(maxTransfer)
 
   // Sanity check the link...
-  require (maxTransfer >= manager.beatBytes)
+  require (maxTransfer >= manager.beatBytes, s"Link's max transfer (${maxTransfer}) < ${manager.managers.map(_.name)}'s beatBytes (${manager.beatBytes})")
 
   val bundle = TLBundleParameters(client, manager)
 }

src/main/scala/tilelink/package.scala

@@ -9,9 +9,13 @@ package object tilelink
 {
   type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
   type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
+  type TLAsyncInwardNode = InwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
   type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
+  type TLRationalInwardNode = InwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
   type TLRationalOutwardNode = OutwardNodeHandle[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]
-  type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
   type TLMixedNode = MixedNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeIn, TLBundle,
                                TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLBundle]
+
+  type IntInwardNode = InwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
+  type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
 }