riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Combine Coreplex and System Module Hierarchies (#875)

Browse Source 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
2017-07-23 08:31:04 -07:00
committed by Yunsup Lee
parent f2002839eb
commit 01ca3efc2b
59 changed files with 1536 additions and 1632 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/tile/L1Cache.scala
View File

@ -21,6 +21,7 @@ trait L1CacheParams {
trait HasL1CacheParameters {
implicit val p: Parameters
val cacheParams: L1CacheParams
private val bundleParams = p(SharedMemoryTLEdge).bundle
def cacheBlockBytes = cacheParams.blockBytes
def lgCacheBlockBytes = log2Up(cacheBlockBytes)
@ -28,7 +29,7 @@ trait HasL1CacheParameters {
def blockOffBits = lgCacheBlockBytes
def idxBits = log2Up(cacheParams.nSets)
def untagBits = blockOffBits + idxBits
def tagBits = p(PAddrBits) - untagBits
def tagBits = bundleParams.addressBits - untagBits
def nWays = cacheParams.nWays
def wayBits = log2Up(nWays)
def isDM = nWays == 1
@ -37,7 +38,7 @@ trait HasL1CacheParameters {
def rowOffBits = log2Up(rowBytes)
def nTLBEntries = cacheParams.nTLBEntries
def cacheDataBits = p(SharedMemoryTLEdge).bundle.dataBits
def cacheDataBits = bundleParams.dataBits
def cacheDataBeats = (cacheBlockBytes * 8) / cacheDataBits
def refillCycles = cacheDataBeats
}