Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/system/TestHarness.scala

@@ -0,0 +1,22 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.system
+
+import Chisel._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.LazyModule
+
+class TestHarness()(implicit p: Parameters) extends Module {
+  val io = new Bundle {
+    val success = Bool(OUTPUT)
+  }
+
+  val dut = Module(LazyModule(new ExampleRocketSystem).module)
+  dut.reset := reset | dut.debug.ndreset
+
+  dut.tieOffInterrupts()
+  dut.connectSimAXIMem()
+  dut.connectSimAXIMMIO()
+  dut.tieOffAXI4SlavePort()
+  dut.connectDebug(clock, reset, io.success)
+}