Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
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@ -105,14 +105,14 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
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// 1) Frontend always exists, but may or may not have a scratchpad node
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val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), earlyAck=true))
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val ww = LazyModule(new TLWidthWidget(xLen/8))
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frontend.slaveNode :*= fg.node
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fg.node :*= ww.node
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ww.node :*= slaveNode
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frontend.slaveNode connectButDontMonitorSlaves fg.node
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fg.node connectButDontMonitorSlaves ww.node
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ww.node connectButDontMonitorSlaves slaveNode
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// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
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val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>
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LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1)))))
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scratch foreach { lm => lm.node := TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
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scratch foreach { lm => lm.node connectButDontMonitor TLFragmenter(xLen/8, p(CacheBlockBytes), earlyAck=true)(slaveNode) }
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def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
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val finalNode = frontend.masterNode.edgesOut.head.manager.managers.find(_.nodePath.last == s.node)
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