Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
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@ -4,15 +4,14 @@
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package freechips.rocketchip.groundtest
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import Chisel._
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import freechips.rocketchip.chip.{BaseConfig, ExtMem}
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import freechips.rocketchip.config.Config
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import freechips.rocketchip.coreplex.{CacheBlockBytes, L1toL2Config, WithBufferlessBroadcastHub}
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
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import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
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/** Actual testing target Configs */
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class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseConfig)
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class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseCoreplexConfig)
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class TraceGenBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new TraceGenConfig)
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@ -26,8 +25,8 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
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addrBag = {
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val nSets = 2
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val nWays = 1
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val blockOffset = log2Up(site(CacheBlockBytes))
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val nBeats = site(CacheBlockBytes)/site(L1toL2Config).beatBytes
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val blockOffset = site(SystemBusParams).blockOffset
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val nBeats = site(SystemBusParams).blockBeats
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
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}.flatten
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