Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/groundtest/Configs.scala

@@ -4,15 +4,14 @@
 package freechips.rocketchip.groundtest
 
 import Chisel._
-import freechips.rocketchip.chip.{BaseConfig, ExtMem}
 import freechips.rocketchip.config.Config
-import freechips.rocketchip.coreplex.{CacheBlockBytes, L1toL2Config, WithBufferlessBroadcastHub}
+import freechips.rocketchip.coreplex._
 import freechips.rocketchip.rocket.{DCacheParams, PAddrBits}
 import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
 
 /** Actual testing target Configs */
 
-class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseConfig)
+class TraceGenConfig extends Config(new WithTraceGen(List.fill(2){ DCacheParams(nSets = 16, nWays = 1) }) ++ new BaseCoreplexConfig)
 
 class TraceGenBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new TraceGenConfig)
 
@@ -26,8 +25,8 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
     addrBag = {
       val nSets = 2
       val nWays = 1
-      val blockOffset = log2Up(site(CacheBlockBytes))
-      val nBeats = site(CacheBlockBytes)/site(L1toL2Config).beatBytes
+      val blockOffset = site(SystemBusParams).blockOffset
+      val nBeats = site(SystemBusParams).blockBeats
       List.tabulate(4 * nWays) { i =>
         Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
       }.flatten

src/main/scala/groundtest/Coreplex.scala

@@ -14,33 +14,43 @@ import scala.math.max
 
 case object TileId extends Field[Int]
 
-class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
+class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
+    with HasMasterAXI4MemPort
+    with HasPeripheryTestRAMSlave {
   val tileParams = p(GroundTestTilesKey)
   val tiles = tileParams.zipWithIndex.map { case(c, i) => LazyModule(
     c.build(i, p.alterPartial {
       case TileKey => c
-      case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
+      case SharedMemoryTLEdge => sbus.edgesIn.head
     })
   )}
 
-  val fixer = LazyModule(new TLFIFOFixer)
-  tile_splitter.node :=* fixer.node
-  tiles.foreach { fixer.node :=* _.masterNode }
+  tiles.foreach { sbus.fromSyncTiles(BufferParams.default) :=* _.masterNode }
 
-  val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBeatBytes))
-  pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
+  val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbus.beatBytes))
+  pbusRAM.node := pbus.toVariableWidthSlaves
 
-  override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
+  override lazy val module = new GroundTestCoreplexModule(this)
 }
 
-class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) {
-  val success = Bool(OUTPUT)
-}
-
-class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) {
+class GroundTestCoreplexModule[+L <: GroundTestCoreplex](_outer: L) extends BaseCoreplexModule(_outer)
+    with HasMasterAXI4MemPortModuleImp {
+  val success = IO(Bool(OUTPUT))
 
   outer.tiles.zipWithIndex.map { case(t, i) => t.module.io.hartid := UInt(i) }
 
   val status = DebugCombiner(outer.tiles.map(_.module.io.status))
-  io.success := status.finished
+  success := status.finished
+}
+
+/** Adds a SRAM to the system for testing purposes. */
+trait HasPeripheryTestRAMSlave extends HasPeripheryBus {
+  val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, pbus.beatBytes))
+  testram.node := pbus.toVariableWidthSlaves
+}
+
+/** Adds a fuzzing master to the system for testing purposes. */
+trait HasPeripheryTestFuzzMaster extends HasPeripheryBus {
+  val fuzzer = LazyModule(new TLFuzzer(5000))
+  pbus.bufferFromMasters := fuzzer.node
 }

src/main/scala/groundtest/TestHarness.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.LazyModule
 
 class TestHarness(implicit p: Parameters) extends Module {
   val io = new Bundle { val success = Bool(OUTPUT) }
-  val dut = Module(LazyModule(new GroundTestTop).module)
-  io.success := dut.io_success
+  val dut = Module(LazyModule(new GroundTestCoreplex).module)
+  io.success := dut.success
   dut.connectSimAXIMem()
 }

src/main/scala/groundtest/Tile.scala

@@ -6,11 +6,8 @@ package freechips.rocketchip.groundtest
 import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.coreplex._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.rocket._
-import freechips.rocketchip.chip._
+import freechips.rocketchip.rocket.{HellaCache, RocketCoreParams}
 import freechips.rocketchip.tile._
-import freechips.rocketchip.tilelink._
 import scala.collection.mutable.ListBuffer
 
 trait GroundTestTileParams extends TileParams {

src/main/scala/groundtest/Top.scala

@@ -1,27 +0,0 @@
-// See LICENSE.SiFive for license details.
-
-package freechips.rocketchip.groundtest
-
-import Chisel._
-
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy.LazyModule
-import freechips.rocketchip.chip._
-
-class GroundTestTop(implicit p: Parameters) extends BaseSystem
-    with HasPeripheryMasterAXI4MemPort
-    with HasPeripheryTestRAMSlave {
-  override lazy val module = new GroundTestTopModule(this)
-
-  val coreplex = LazyModule(new GroundTestCoreplex)
-
-  socBus.node := coreplex.mmio
-  coreplex.mmioInt := intBus.intnode
-  (mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
-}
-
-class GroundTestTopModule[+L <: GroundTestTop](_outer: L) extends BaseSystemModule(_outer)
-    with HasPeripheryMasterAXI4MemPortModuleImp {
-  val io_success = IO(Bool(OUTPUT))
-  io_success := outer.coreplex.module.io.success
-}