Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/devices/tilelink/Zero.scala

@@ -3,7 +3,8 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.HasMemoryBus
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
@@ -44,3 +45,23 @@ class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean
     in.e.ready := Bool(true)
   }
 }
+
+/* Specifies the location of the Zero device */
+case class ZeroParams(base: Long, size: Long, beatBytes: Int)
+case object ZeroParams extends Field[ZeroParams]
+
+/** Adds a /dev/null slave that generates zero-filled responses to reads */
+trait HasMemoryZeroSlave extends HasMemoryBus {
+  private val params = p(ZeroParams)
+  private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
+
+  val zeros = memBuses.map(_.toVariableWidthSlave).zipWithIndex.map { case (node, channel) =>
+    val channels = memBuses.size
+    val base = AddressSet(params.base, params.size-1)
+    val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
+    val address = base.intersect(filter).get
+    val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
+    zero.node := node
+    zero
+  }
+}