Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/devices/tilelink/Plic.scala

@@ -4,7 +4,8 @@ package freechips.rocketchip.devices.tilelink
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tile.XLen
@@ -57,6 +58,8 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7)
   def address = AddressSet(baseAddress, PLICConsts.size-1)
 }
 
+case object PLICParams extends Field[PLICParams]
+
 /** Platform-Level Interrupt Controller */
 class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
 {
@@ -232,3 +235,10 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
       e(0) := false
   }
 }
+
+/** Trait that will connect a PLIC to a coreplex */
+trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
+  val plic  = LazyModule(new TLPLIC(p(PLICParams)))
+  plic.node := pbus.toVariableWidthSlaves
+  plic.intnode := ibus.toPLIC
+}