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Combine Coreplex and System Module Hierarchies (#875)

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* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
2017-07-23 08:31:04 -07:00
committed by Yunsup Lee
parent f2002839eb
commit 01ca3efc2b
59 changed files with 1536 additions and 1632 deletions
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22
src/main/scala/devices/tilelink/Error.scala
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@ -3,13 +3,21 @@
package freechips.rocketchip.devices.tilelink
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import scala.math.min
class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
case class ErrorParams(address: Seq[AddressSet])
case object ErrorParams extends Field[ErrorParams]
/** Adds a /dev/null slave that generates TL error response messages */
class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
{
val address = params.address
val device = new SimpleDevice("error-device", Seq("sifive,error0"))
val node = TLManagerNode(Seq(TLManagerPortParameters(
@ -55,3 +63,13 @@ class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Paramete
in.e.ready := Bool(true)
}
}
trait HasPeripheryErrorSlave extends HasPeripheryBus {
private val params = p(ErrorParams)
private val maxXfer = min(params.address.map(_.alignment).max.toInt, 4096)
val error = LazyModule(new TLError(params, pbus.beatBytes))
// Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others;
// we exclude the onerously large TLMonitor that results.
error.node connectButDontMonitor pbus.toLargeBurstSlave(maxXfer)
}