Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/devices/tilelink/BootROM.scala

@@ -0,0 +1,41 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.devices.tilelink
+
+import Chisel._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import java.nio.{ByteBuffer, ByteOrder}
+import java.nio.file.{Files, Paths}
+
+/** Size, location and contents of the boot rom. */
+case class BootROMParams(
+  address: BigInt = 0x10000,
+  size: Int = 0x10000,
+  hang: BigInt = 0x10040,
+  contentFileName: String)
+case object BootROMParams extends Field[BootROMParams]
+
+/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
+trait HasPeripheryBootROM extends HasPeripheryBus {
+  val dtb: DTB
+  private val params = p(BootROMParams)
+  private lazy val contents = {
+    val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
+    val rom = ByteBuffer.wrap(romdata)
+    rom.array() ++ dtb.contents
+  }
+  def resetVector: BigInt = params.hang
+
+  val bootrom = LazyModule(new TLROM(params.address, params.size, contents, true, pbus.beatBytes))
+
+  bootrom.node := pbus.toVariableWidthSlaves
+}
+
+/** Coreplex will power-on running at 0x10040 (BootROM) */
+trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp
+    with HasResetVectorWire {
+  val outer: HasPeripheryBootROM
+  global_reset_vector := UInt(outer.resetVector, width = resetVectorBits)
+}

src/main/scala/devices/tilelink/Clint.scala

@@ -3,7 +3,8 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.HasPeripheryBus
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tile.XLen
@@ -29,6 +30,8 @@ case class ClintParams(baseAddress: BigInt = 0x02000000)
   def address = AddressSet(baseAddress, ClintConsts.size-1)
 }
 
+case object ClintParams extends Field[ClintParams]
+
 class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
 {
   import ClintConsts._
@@ -90,3 +93,9 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
       timeOffset       -> makeRegFields(time))
   }
 }
+
+/** Trait that will connect a Clint to a coreplex */
+trait HasPeripheryClint extends HasPeripheryBus {
+  val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintParams)))
+  clint.node := pbus.toVariableWidthSlaves
+}

src/main/scala/devices/tilelink/Error.scala

@@ -3,13 +3,21 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.HasPeripheryBus
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
+import scala.math.min
 
-class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
+case class ErrorParams(address: Seq[AddressSet])
+case object ErrorParams extends Field[ErrorParams]
+
+/** Adds a /dev/null slave that generates TL error response messages */
+class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
 {
+  val address = params.address
+
   val device = new SimpleDevice("error-device", Seq("sifive,error0"))
 
   val node = TLManagerNode(Seq(TLManagerPortParameters(
@@ -55,3 +63,13 @@ class TLError(address: Seq[AddressSet], beatBytes: Int = 4)(implicit p: Paramete
     in.e.ready := Bool(true)
   }
 }
+
+trait HasPeripheryErrorSlave extends HasPeripheryBus {
+  private val params = p(ErrorParams)
+  private val maxXfer = min(params.address.map(_.alignment).max.toInt, 4096)
+  val error = LazyModule(new TLError(params, pbus.beatBytes))
+
+  // Most slaves do not support a 4kB burst so this slave ends up with many more source bits than others;
+  // we exclude the onerously large TLMonitor that results.
+  error.node connectButDontMonitor pbus.toLargeBurstSlave(maxXfer)
+}

src/main/scala/devices/tilelink/Plic.scala

@@ -4,7 +4,8 @@ package freechips.rocketchip.devices.tilelink
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tile.XLen
@@ -57,6 +58,8 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7)
   def address = AddressSet(baseAddress, PLICConsts.size-1)
 }
 
+case object PLICParams extends Field[PLICParams]
+
 /** Platform-Level Interrupt Controller */
 class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
 {
@@ -232,3 +235,10 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
       e(0) := false
   }
 }
+
+/** Trait that will connect a PLIC to a coreplex */
+trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
+  val plic  = LazyModule(new TLPLIC(p(PLICParams)))
+  plic.node := pbus.toVariableWidthSlaves
+  plic.intnode := ibus.toPLIC
+}

src/main/scala/devices/tilelink/Zero.scala

@@ -3,7 +3,8 @@
 package freechips.rocketchip.devices.tilelink
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.coreplex.HasMemoryBus
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
@@ -44,3 +45,23 @@ class TLZero(address: AddressSet, resources: Seq[Resource], executable: Boolean
     in.e.ready := Bool(true)
   }
 }
+
+/* Specifies the location of the Zero device */
+case class ZeroParams(base: Long, size: Long, beatBytes: Int)
+case object ZeroParams extends Field[ZeroParams]
+
+/** Adds a /dev/null slave that generates zero-filled responses to reads */
+trait HasMemoryZeroSlave extends HasMemoryBus {
+  private val params = p(ZeroParams)
+  private val device = new SimpleDevice("rom", Seq("ucbbar,cacheable-zero0"))
+
+  val zeros = memBuses.map(_.toVariableWidthSlave).zipWithIndex.map { case (node, channel) =>
+    val channels = memBuses.size
+    val base = AddressSet(params.base, params.size-1)
+    val filter = AddressSet(channel * cacheBlockBytes, ~((channels-1) * cacheBlockBytes))
+    val address = base.intersect(filter).get
+    val zero = LazyModule(new TLZero(address, beatBytes = params.beatBytes, resources = device.reg("mem")))
+    zero.node := node
+    zero
+  }
+}