riscv/rocket-chip
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Combine Coreplex and System Module Hierarchies (#875)

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* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
2017-07-23 08:31:04 -07:00
committed by Yunsup Lee
parent f2002839eb
commit 01ca3efc2b
59 changed files with 1536 additions and 1632 deletions
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18
src/main/scala/devices/debug/Debug.scala
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@ -61,11 +61,11 @@ object DsbRegAddrs{
// We want DATA to immediately follow PROGBUF so that we can
// use them interchangeably.
def PROGBUF(cfg:DebugModuleConfig) = {DATA - (cfg.nProgramBufferWords * 4)}
def PROGBUF(cfg:DebugModuleParams) = {DATA - (cfg.nProgramBufferWords * 4)}
// We want abstract to be immediately before PROGBUF
// because we auto-generate 2 instructions.
def ABSTRACT(cfg:DebugModuleConfig) = PROGBUF(cfg) - 8
def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - 8
def FLAGS = 0x400
def ROMBASE = 0x800
@ -112,7 +112,7 @@ import DebugAbstractCommandType._
* supportHartArray : Whether or not to implement the hart array register.
**/
case class DebugModuleConfig (
case class DebugModuleParams (
nDMIAddrSize : Int = 7,
nProgramBufferWords: Int = 16,
nAbstractDataWords : Int = 4,
@ -152,17 +152,17 @@ case class DebugModuleConfig (
}
object DefaultDebugModuleConfig {
object DefaultDebugModuleParams {
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleConfig = {
new DebugModuleConfig().copy(
def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
new DebugModuleParams().copy(
nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4)
)
}
}
case object DMKey extends Field[DebugModuleConfig]
case object DebugModuleParams extends Field[DebugModuleParams]
// *****************************************
// Module Interfaces
@ -192,7 +192,7 @@ class DMIResp( ) extends Bundle {
* Therefore it has the 'flipped' version of this.
*/
class DMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
val req = new DecoupledIO(new DMIReq(p(DMKey).nDMIAddrSize))
val req = new DecoupledIO(new DMIReq(p(DebugModuleParams).nDMIAddrSize))
val resp = new DecoupledIO(new DMIResp).flip()
}
@ -443,7 +443,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
lazy val module = new LazyModuleImp(this){
val cfg = p(DMKey)
val cfg = p(DebugModuleParams)
val nComponents = getNComponents()