Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
Yunsup Lee
@ -61,11 +61,11 @@ object DsbRegAddrs{
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// We want DATA to immediately follow PROGBUF so that we can
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// use them interchangeably.
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def PROGBUF(cfg:DebugModuleConfig) = {DATA - (cfg.nProgramBufferWords * 4)}
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def PROGBUF(cfg:DebugModuleParams) = {DATA - (cfg.nProgramBufferWords * 4)}
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// We want abstract to be immediately before PROGBUF
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// because we auto-generate 2 instructions.
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def ABSTRACT(cfg:DebugModuleConfig) = PROGBUF(cfg) - 8
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def ABSTRACT(cfg:DebugModuleParams) = PROGBUF(cfg) - 8
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def FLAGS = 0x400
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def ROMBASE = 0x800
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@ -112,7 +112,7 @@ import DebugAbstractCommandType._
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* supportHartArray : Whether or not to implement the hart array register.
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**/
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case class DebugModuleConfig (
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case class DebugModuleParams (
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nDMIAddrSize : Int = 7,
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nProgramBufferWords: Int = 16,
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nAbstractDataWords : Int = 4,
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@ -152,17 +152,17 @@ case class DebugModuleConfig (
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}
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object DefaultDebugModuleConfig {
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object DefaultDebugModuleParams {
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def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleConfig = {
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new DebugModuleConfig().copy(
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def apply(xlen:Int /*TODO , val configStringAddr: Int*/): DebugModuleParams = {
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new DebugModuleParams().copy(
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nAbstractDataWords = (if (xlen == 32) 1 else if (xlen == 64) 2 else 4)
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)
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}
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}
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case object DMKey extends Field[DebugModuleConfig]
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case object DebugModuleParams extends Field[DebugModuleParams]
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// *****************************************
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// Module Interfaces
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@ -192,7 +192,7 @@ class DMIResp( ) extends Bundle {
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* Therefore it has the 'flipped' version of this.
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*/
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class DMIIO(implicit val p: Parameters) extends ParameterizedBundle()(p) {
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val req = new DecoupledIO(new DMIReq(p(DMKey).nDMIAddrSize))
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val req = new DecoupledIO(new DMIReq(p(DebugModuleParams).nDMIAddrSize))
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val resp = new DecoupledIO(new DMIResp).flip()
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}
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@ -443,7 +443,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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lazy val module = new LazyModuleImp(this){
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val cfg = p(DMKey)
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val cfg = p(DebugModuleParams)
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val nComponents = getNComponents()
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262
src/main/scala/devices/debug/DebugTransport.scala
Normal file
262
src/main/scala/devices/debug/DebugTransport.scala
Normal file
@ -0,0 +1,262 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.devices.debug
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.jtag._
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import freechips.rocketchip.util._
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case class JtagDTMConfig (
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idcodeVersion : Int, // chosen by manuf.
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idcodePartNum : Int, // Chosen by manuf.
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idcodeManufId : Int, // Assigned by JEDEC
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// Note: the actual manufId is passed in through a wire.
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// Do not forget to wire up io.jtag_mfr_id through your top-level to set the
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// mfr_id for this core.
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// If you wish to use this field in the config, you can obtain it along
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// the lines of p(JtagDTMKey).idcodeManufId.U(11.W).
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debugIdleCycles : Int)
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case object JtagDTMKey extends Field[JtagDTMConfig]
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class JtagDTMKeyDefault extends JtagDTMConfig(
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idcodeVersion = 0,
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idcodePartNum = 0,
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idcodeManufId = 0,
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debugIdleCycles = 5) // Reasonable guess for synchronization.
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object dtmJTAGAddrs {
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def IDCODE = 0x1
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def DTM_INFO = 0x10
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def DMI_ACCESS = 0x11
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}
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class DMIAccessUpdate(addrBits: Int) extends Bundle {
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val addr = UInt(width = addrBits)
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val data = UInt(width = DMIConsts.dmiDataSize)
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val op = UInt(width = DMIConsts.dmiOpSize)
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override def cloneType = new DMIAccessUpdate(addrBits).asInstanceOf[this.type]
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}
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class DMIAccessCapture(addrBits: Int) extends Bundle {
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val addr = UInt(width = addrBits)
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val data = UInt(width = DMIConsts.dmiDataSize)
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val resp = UInt(width = DMIConsts.dmiRespSize)
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override def cloneType = new DMIAccessCapture(addrBits).asInstanceOf[this.type]
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}
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class DTMInfo extends Bundle {
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val reserved1 = UInt(15.W)
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val dmireset = Bool()
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val reserved0 = UInt(1.W)
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val dmiIdleCycles = UInt(3.W)
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val dmiStatus = UInt(2.W)
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val debugAddrBits = UInt(6.W)
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val debugVersion = UInt(4.W)
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}
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/** A wrapper around JTAG providing a reset signal and manufacturer id. */
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class SystemJTAGIO extends Bundle {
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val jtag = new JTAGIO(hasTRSTn = false).flip
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val reset = Bool(INPUT)
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val mfr_id = UInt(INPUT, 11)
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}
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class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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(implicit val p: Parameters) extends Module {
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val io = new Bundle {
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val dmi = new DMIIO()(p)
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val jtag = Flipped(new JTAGIO(hasTRSTn = false)) // TODO: re-use SystemJTAGIO here?
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val jtag_reset = Bool(INPUT)
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val jtag_mfr_id = UInt(INPUT, 11)
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val fsmReset = Bool(OUTPUT)
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}
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//--------------------------------------------------------
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// Reg and Wire Declarations
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val dtmInfo = Wire(new DTMInfo)
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val busyReg = RegInit(Bool(false))
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val stickyBusyReg = RegInit(Bool(false))
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val stickyNonzeroRespReg = RegInit(Bool(false))
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val skipOpReg = Reg(init = Bool(false)) // Skip op because we're busy
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val downgradeOpReg = Reg(init = Bool(false)) // downgrade op because prev. failed.
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val busy = Wire(Bool())
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val nonzeroResp = Wire(Bool())
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val busyResp = Wire(new DMIAccessCapture(debugAddrBits))
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val nonbusyResp = Wire(new DMIAccessCapture(debugAddrBits))
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val dmiResp = Wire(new DMIAccessCapture(debugAddrBits))
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val nopResp = Wire(new DMIAccessCapture(debugAddrBits))
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val dmiReqReg = Reg(new DMIReq(debugAddrBits))
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val dmiReqValidReg = Reg(init = Bool(false));
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val dmiStatus = Wire(UInt(width = 2))
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//--------------------------------------------------------
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// DTM Info Chain Declaration
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dmiStatus := Cat(stickyNonzeroRespReg, stickyNonzeroRespReg | stickyBusyReg)
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dtmInfo.debugVersion := 1.U // This implements version 1 of the spec.
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dtmInfo.debugAddrBits := UInt(debugAddrBits)
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dtmInfo.dmiStatus := dmiStatus
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dtmInfo.dmiIdleCycles := UInt(c.debugIdleCycles)
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dtmInfo.reserved0 := 0.U
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dtmInfo.dmireset := false.B // This is write-only
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dtmInfo.reserved1 := 0.U
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val dtmInfoChain = Module (CaptureUpdateChain(gen = new DTMInfo()))
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dtmInfoChain.io.capture.bits := dtmInfo
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//--------------------------------------------------------
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// Debug Access Chain Declaration
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val dmiAccessChain = Module(CaptureUpdateChain(genCapture = new DMIAccessCapture(debugAddrBits),
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genUpdate = new DMIAccessUpdate(debugAddrBits)))
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//--------------------------------------------------------
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// Debug Access Support
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// Busy Register. We become busy when we first try to send a request.
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// We stop being busy when we accept a response.
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when (io.dmi.req.valid) {
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busyReg := Bool(true)
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}
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when (io.dmi.resp.fire()) {
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busyReg := Bool(false)
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}
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// We are busy during a given CAPTURE
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// if we haven't received a valid response yet or if we
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// were busy last time without a reset.
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// busyReg will still be set when we check it,
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// so the logic for checking busy looks ahead.
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busy := (busyReg & !io.dmi.resp.valid) | stickyBusyReg;
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// Downgrade/Skip. We make the decision to downgrade or skip
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// during every CAPTURE_DR, and use the result in UPDATE_DR.
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// The sticky versions are reset by write to dmiReset in DTM_INFO.
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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}
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when (dtmInfoChain.io.update.valid) {
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when (dtmInfoChain.io.update.bits.dmireset) {
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stickyNonzeroRespReg := Bool(false)
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stickyBusyReg := Bool(false)
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}
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}
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// Especially for the first request, we must consider dtmResp.valid,
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// so that we don't consider junk in the FIFO to be an error response.
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// The current specification says that any non-zero response is an error.
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// But there is actually no case in the current design where you SHOULD get an error,
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// as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors
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// can occur.
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nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0)))
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assert(!nonzeroResp, "There is no reason to get a non zero response in the current system.");
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assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system.");
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busyResp.addr := UInt(0)
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busyResp.resp := Fill(DMIConsts.dmiRespSize, 1.U) // Generalizing busy to 'all-F'
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busyResp.data := UInt(0)
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dmiResp.addr := dmiReqReg.addr
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dmiResp.resp := io.dmi.resp.bits.resp
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dmiResp.data := io.dmi.resp.bits.data
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nopResp.addr := UInt(0)
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nopResp.resp := UInt(0)
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nopResp.data := UInt(0)
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//--------------------------------------------------------
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// Debug Access Chain Implementation
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dmiAccessChain.io.capture.bits := Mux(busy, busyResp, Mux(io.dmi.resp.valid, dmiResp, nopResp))
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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}
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//--------------------------------------------------------
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// Drive Ready Valid Interface
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val dmiReqValidCheck = Wire(init = Bool(false))
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assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
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when (dmiAccessChain.io.update.valid) {
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when (skipOpReg) {
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// Do Nothing
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}.elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
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//Do Nothing
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dmiReqReg.addr := UInt(0)
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dmiReqReg.data := UInt(0)
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dmiReqReg.op := UInt(0)
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}.otherwise {
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dmiReqReg := dmiAccessChain.io.update.bits
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dmiReqValidReg := Bool(true)
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dmiReqValidCheck := Bool(true)
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}
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}
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when (io.dmi.req.fire()) {
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dmiReqValidReg := Bool(false)
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}
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io.dmi.resp.ready := dmiAccessChain.io.capture.capture
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io.dmi.req.valid := dmiReqValidReg
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// This is a name-based, not type-based assignment. Do these still work?
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io.dmi.req.bits := dmiReqReg
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//--------------------------------------------------------
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// Actual JTAG TAP
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val idcode = Wire(init = new JTAGIdcodeBundle().fromBits(0.U))
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idcode.always1 := 1.U
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idcode.version := c.idcodeVersion.U
|
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idcode.partNumber := c.idcodePartNum.U
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idcode.mfrId := io.jtag_mfr_id
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|
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val tapIO = JtagTapGenerator(irLength = 5,
|
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instructions = Map(dtmJTAGAddrs.DMI_ACCESS -> dmiAccessChain,
|
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dtmJTAGAddrs.DTM_INFO -> dtmInfoChain),
|
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icode = Some(dtmJTAGAddrs.IDCODE)
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)
|
||||
|
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tapIO.idcode.get := idcode
|
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tapIO.jtag <> io.jtag
|
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|
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tapIO.control.jtag_reset := io.jtag_reset
|
||||
|
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//--------------------------------------------------------
|
||||
// Reset Generation (this is fed back to us by the instantiating module,
|
||||
// and is used to reset the debug registers).
|
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|
||||
io.fsmReset := tapIO.output.reset
|
||||
|
||||
}
|
||||
123
src/main/scala/devices/debug/Periphery.scala
Normal file
123
src/main/scala/devices/debug/Periphery.scala
Normal file
@ -0,0 +1,123 @@
|
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// See LICENSE.SiFive for license details.
|
||||
|
||||
package freechips.rocketchip.devices.debug
|
||||
|
||||
import Chisel._
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.coreplex.HasPeripheryBus
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.jtag._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
/** A knob selecting one of the two possible debug interfaces */
|
||||
case object IncludeJtagDTM extends Field[Boolean]
|
||||
|
||||
/** A wrapper bundle containing one of the two possible debug interfaces */
|
||||
class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
|
||||
val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
|
||||
val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
|
||||
val ndreset = Bool(OUTPUT)
|
||||
val dmactive = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
|
||||
* or exports the Debug Module Interface (DMI), based on a global parameter.
|
||||
*/
|
||||
trait HasPeripheryDebug extends HasPeripheryBus {
|
||||
val module: HasPeripheryDebugModuleImp
|
||||
|
||||
val debug = LazyModule(new TLDebugModule())
|
||||
|
||||
debug.node := pbus.toVariableWidthSlaves
|
||||
}
|
||||
|
||||
trait HasPeripheryDebugBundle {
|
||||
implicit val p: Parameters
|
||||
|
||||
val debug: DebugIO
|
||||
|
||||
def connectDebug(c: Clock, r: Bool, out: Bool) {
|
||||
debug.clockeddmi.foreach { d =>
|
||||
val dtm = Module(new SimDTM).connect(c, r, d, out)
|
||||
}
|
||||
debug.systemjtag.foreach { sj =>
|
||||
val jtag = Module(new JTAGVPI).connect(sj.jtag, sj.reset, r, out)
|
||||
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
|
||||
val outer: HasPeripheryDebug
|
||||
|
||||
val debug = IO(new DebugIO)
|
||||
|
||||
debug.clockeddmi.foreach { dbg => outer.debug.module.io.dmi <> dbg }
|
||||
|
||||
val dtm = debug.systemjtag.map { sj =>
|
||||
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleParams).nDMIAddrSize, p(JtagDTMKey)))
|
||||
dtm.io.jtag <> sj.jtag
|
||||
|
||||
dtm.clock := sj.jtag.TCK
|
||||
dtm.io.jtag_reset := sj.reset
|
||||
dtm.io.jtag_mfr_id := sj.mfr_id
|
||||
dtm.reset := dtm.io.fsmReset
|
||||
|
||||
outer.debug.module.io.dmi.dmi <> dtm.io.dmi
|
||||
outer.debug.module.io.dmi.dmiClock := sj.jtag.TCK
|
||||
outer.debug.module.io.dmi.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch")
|
||||
dtm
|
||||
}
|
||||
|
||||
debug.ndreset := outer.debug.module.io.ctrl.ndreset
|
||||
debug.dmactive := outer.debug.module.io.ctrl.dmactive
|
||||
|
||||
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
|
||||
outer.debug.module.io.ctrl.debugUnavail.foreach { _ := Bool(false) }
|
||||
}
|
||||
|
||||
class SimDTM(implicit p: Parameters) extends BlackBox {
|
||||
val io = new Bundle {
|
||||
val clk = Clock(INPUT)
|
||||
val reset = Bool(INPUT)
|
||||
val debug = new DMIIO
|
||||
val exit = UInt(OUTPUT, 32)
|
||||
}
|
||||
|
||||
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
|
||||
io.clk := tbclk
|
||||
io.reset := tbreset
|
||||
dutio.dmi <> io.debug
|
||||
dutio.dmiClock := tbclk
|
||||
dutio.dmiReset := tbreset
|
||||
|
||||
tbsuccess := io.exit === UInt(1)
|
||||
when (io.exit >= UInt(2)) {
|
||||
printf("*** FAILED *** (exit code = %d)\n", io.exit >> UInt(1))
|
||||
stop(1)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
class JTAGVPI(implicit val p: Parameters) extends BlackBox {
|
||||
val io = new Bundle {
|
||||
val jtag = new JTAGIO(hasTRSTn = false)
|
||||
val enable = Bool(INPUT)
|
||||
val init_done = Bool(INPUT)
|
||||
}
|
||||
|
||||
def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = {
|
||||
dutio <> io.jtag
|
||||
|
||||
dutio.TRSTn.foreach{ _:= false.B}
|
||||
jtag_reset := tbreset
|
||||
|
||||
io.enable := ~tbreset
|
||||
io.init_done := ~tbreset
|
||||
|
||||
// Success is determined by the gdbserver
|
||||
// which is controlling this simulation.
|
||||
tbsuccess := Bool(false)
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user