Combine Coreplex and System Module Hierarchies (#875)

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

src/main/scala/coreplex/PeripheryBus.scala

@@ -0,0 +1,48 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.coreplex
+
+import Chisel._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+case class PeripheryBusParams(
+  beatBytes: Int,
+  blockBytes: Int,
+  masterBuffering: BufferParams = BufferParams.default,
+  slaveBuffering: BufferParams = BufferParams.none,
+  arithmetic: Boolean = true
+) extends TLBusParams {
+}
+
+case object PeripheryBusParams extends Field[PeripheryBusParams]
+
+class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
+  def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
+    TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
+  }
+
+  def toLargeBurstSlave(maxXferBytes: Int) = {
+    TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
+  }
+
+  val fromSystemBus: TLInwardNode = {
+    val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
+    inwardBufNode := atomics.node
+    atomics.node
+  }
+}
+
+/** Provides buses that serve as attachment points,
+  * for use in traits that connect individual devices or external ports.
+  */
+trait HasPeripheryBus extends HasSystemBus {
+  private val pbusParams = p(PeripheryBusParams)
+  val pbusBeatBytes = pbusParams.beatBytes
+
+  val pbus = new PeripheryBus(pbusParams)
+
+  // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
+  pbus.fromSystemBus := sbus.toPeripheryBus
+}