Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
This commit is contained in:
Henry Cook
Yunsup Lee
@@ -4,7 +4,6 @@
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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@@ -15,6 +14,7 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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class BaseCoreplexConfig extends Config ((site, here, up) => {
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// Tile parameters
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case PAddrBits => 32
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 0
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@@ -22,19 +22,26 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
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case ResetVectorBits => site(PAddrBits)
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case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
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case BuildCore => (p: Parameters) => new Rocket()(p)
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case RocketTilesKey => Nil // Will be added by partial configs found below
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// Interconnect parameters
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case RocketCrossing => SynchronousCrossing()
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case RocketTilesKey => Nil
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case DMKey => DefaultDebugModuleConfig(site(XLen))
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case PLICKey => PLICParams()
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case ClintKey => ClintParams()
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case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
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case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
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case BootROMFile => "./bootrom/bootrom.img"
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case BroadcastConfig => BroadcastConfig()
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case BankedL2Config => BankedL2Config()
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case BroadcastParams => BroadcastParams()
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case BankedL2Params => BankedL2Params()
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case SystemBusParams => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case PeripheryBusParams => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case MemoryBusParams => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes))
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case CacheBlockBytes => 64
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// Device parameters
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case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
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case PLICParams => PLICParams()
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case ClintParams => ClintParams()
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// TileLink connection global parameters
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case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
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case TLCombinationalCheck => false
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})
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/* Composable partial function Configs to set individual parameters */
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class WithNBigCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => {
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val big = RocketTileParams(
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@@ -43,11 +50,11 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
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mulEarlyOut = true,
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divEarlyOut = true))),
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dcache = Some(DCacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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nMSHRs = 0,
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rowBits = site(SystemBusParams).beatBits,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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rowBits = site(SystemBusParams).beatBits,
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blockBytes = site(CacheBlockBytes))))
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List.fill(n)(big) ++ up(RocketTilesKey, site)
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}
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@@ -59,14 +66,14 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
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core = RocketCoreParams(useVM = false, fpu = None),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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rowBits = site(SystemBusParams).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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rowBits = site(SystemBusParams).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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@@ -75,12 +82,39 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
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}
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})
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class WithNTinyCores(n: Int) extends Config((site, here, up) => {
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case XLen => 32
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case RocketTilesKey => {
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val tiny = RocketTileParams(
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core = RocketCoreParams(
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useVM = false,
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fpu = None,
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mulDiv = Some(MulDivParams(mulUnroll = 8))),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusParams).beatBits,
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nSets = 256, // 16Kb scratchpad
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes),
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scratch = Some(0x80000000L))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusParams).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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blockBytes = site(CacheBlockBytes))))
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List.fill(n)(tiny) ++ up(RocketTilesKey, site)
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}
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})
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class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
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case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
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case BankedL2Params => up(BankedL2Params, site).copy(nBanksPerChannel = n)
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})
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class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
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case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
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case BroadcastParams => up(BroadcastParams, site).copy(nTrackers = n)
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})
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// This is the number of icache sets for all Rocket tiles
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@@ -112,7 +146,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
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})
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class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
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case BroadcastParams => up(BroadcastParams, site).copy(bufferless = true)
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})
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/**
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@@ -128,12 +162,10 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config((site, here, up) => {
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
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case BankedL2Params => up(BankedL2Params, site).copy(coherenceManager = { case (q, _) =>
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implicit val p = q
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val cork = LazyModule(new TLCacheCork(unsafe = true))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= cork.node
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(cork.node, ww.node)
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(cork.node, cork.node)
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})
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})
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@@ -208,7 +240,7 @@ class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
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})
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class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
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case BootROMFile => bootROMFile
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case BootROMParams => up(BootROMParams, site).copy(contentFileName = bootROMFile)
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})
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class WithSynchronousRocketTiles extends Config((site, here, up) => {
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@@ -223,3 +255,49 @@ class WithRationalRocketTiles extends Config((site, here, up) => {
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case RocketCrossing => RationalCrossing()
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})
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class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
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case MemoryBusParams => up(MemoryBusParams, site).copy(beatBytes = dataBits/8)
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case ExtIn => up(ExtIn, site).copy(beatBytes = dataBits/8)
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})
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class WithJtagDTM extends Config ((site, here, up) => {
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case IncludeJtagDTM => true
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})
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class WithNoPeripheryArithAMO extends Config ((site, here, up) => {
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case PeripheryBusParams => up(PeripheryBusParams, site).copy(arithmetic = false)
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})
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class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => {
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case PeripheryBusParams => up(PeripheryBusParams, site).copy(beatBytes = nBits/8)
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})
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class WithoutTLMonitors extends Config ((site, here, up) => {
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case TLMonitorBuilder => (args: TLMonitorArgs) => None
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})
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class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
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case NExtTopInterrupts => nExtInts
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})
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class WithRTCPeriod(nCycles: Int) extends Config((site, here, up) => {
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case RTCPeriod => nCycles
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})
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class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
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case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n)
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})
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class WithExtMemSize(n: Long) extends Config((site, here, up) => {
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case ExtMem => up(ExtMem, site).copy(size = n)
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})
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class WithDTS(model: String, compat: Seq[String]) extends Config((site, here, up) => {
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case DTSModel => model
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case DTSCompat => compat
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})
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class WithTimebase(hertz: BigInt) extends Config((site, here, up) => {
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case DTSTimebase => hertz
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})
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