Combine Coreplex and System Module Hierarchies (#875)
* coreplex collapse: peripherals now in coreplex * coreplex: better factoring of TLBusWrapper attachement points * diplomacy: allow monitorless :*= and :=* * rocket: don't connect monitors to tile tim slave ports * rename chip package to system * coreplex: only sbus has a splitter * TLFragmenter: Continuing my spot battles on requires without explanatory strings * pbus: toFixedWidthSingleBeatSlave * tilelink: more verbose requires * use the new system package for regression * sbus: add more explicit FIFO attachment points * delete leftover top-level utils * cleanup ResetVector and RTC
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@ -3,83 +3,133 @@
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tile.{ XLen, TileInterrupts}
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import freechips.rocketchip.rocket.PAddrBits
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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/** Widths of various points in the SoC */
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case class TLBusConfig(beatBytes: Int)
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case object CBusConfig extends Field[TLBusConfig]
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case object L1toL2Config extends Field[TLBusConfig]
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait CoreplexClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 2) extends CoreplexClockCrossing
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// These parameters apply to all caches, for now
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case object CacheBlockBytes extends Field[Int]
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/** L2 Broadcast Hub configuration */
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case class BroadcastConfig(
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nTrackers: Int = 4,
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bufferless: Boolean = false)
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case object BroadcastConfig extends Field[BroadcastConfig]
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/** L2 memory subsystem configuration */
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case class BankedL2Config(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
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implicit val p = q
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val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
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val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= bh.node
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(bh.node, ww.node)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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case object BankedL2Config extends Field[BankedL2Config]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val tilesParams = p(RocketTilesKey)
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lazy val sbusConfig = p(L1toL2Config)
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lazy val pbusConfig = p(CBusConfig)
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lazy val nTiles = tilesParams.size
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lazy val l2Config = p(BankedL2Config)
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def sbusBeatBytes = sbusConfig.beatBytes
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def sbusBlockBytes = p(CacheBlockBytes)
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def pbusBeatBytes = pbusConfig.beatBytes
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def pbusBlockBytes = sbusBlockBytes
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/** BareCoreplex is the root class for creating a coreplex sub-system */
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {
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lazy val dts = DTS(bindingTree)
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lazy val dtb = DTB(dts)
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lazy val json = JSON(bindingTree)
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}
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope
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abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) {
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abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMultiIOModuleImp(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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val io = _io ()
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ElaborationArtefacts.add("graphml", outer.graphML)
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ElaborationArtefacts.add("dts", outer.dts)
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ElaborationArtefacts.add("json", outer.json)
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println(outer.dts)
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}
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/** Base Coreplex class with no peripheral devices or ports added */
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abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
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with CoreplexNetwork
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with BankedL2CoherenceManagers {
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override lazy val module = new BaseCoreplexModule(this, () => new BaseCoreplexBundle(this))
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with HasInterruptBus
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with HasSystemBus
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with HasPeripheryBus
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with HasMemoryBus {
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override val module: BaseCoreplexModule[BaseCoreplex]
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val root = new Device {
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def describe(resources: ResourceBindings): Description = {
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val width = resources("width").map(_.value)
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Description("/", Map(
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"#address-cells" -> width,
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"#size-cells" -> width,
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"model" -> Seq(ResourceString(p(DTSModel))),
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"compatible" -> (p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-dev"))))
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}
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}
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val soc = new Device {
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def describe(resources: ResourceBindings): Description = {
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val width = resources("width").map(_.value)
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Description("soc", Map(
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"#address-cells" -> width,
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"#size-cells" -> width,
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"compatible" -> ((p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")) :+ ResourceString("simple-bus")),
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"ranges" -> Nil))
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}
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}
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val cpus = new Device {
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def describe(resources: ResourceBindings): Description = {
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Description("cpus", Map(
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"#address-cells" -> Seq(ResourceInt(1)),
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"#size-cells" -> Seq(ResourceInt(0)),
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"timebase-frequency" -> Seq(ResourceInt(p(DTSTimebase)))))
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}
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}
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// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
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lazy val topManagers = Some(ManagerUnification(sharedMemoryTLEdge.manager.managers))
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ResourceBinding {
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val managers = topManagers.get
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val max = managers.flatMap(_.address).map(_.max).max
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val width = ResourceInt((log2Ceil(max)+31) / 32)
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Resource(root, "width").bind(width)
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Resource(soc, "width").bind(width)
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Resource(cpus, "null").bind(ResourceString(""))
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managers.foreach { case manager =>
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val value = manager.toResource
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manager.resources.foreach { case resource =>
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resource.bind(value)
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}
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}
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}
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}
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class BaseCoreplexBundle[+L <: BaseCoreplex](_outer: L) extends BareCoreplexBundle(_outer)
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with CoreplexNetworkBundle
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with BankedL2CoherenceManagersBundle
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abstract class BaseCoreplexModule[+L <: BaseCoreplex](_outer: L) extends BareCoreplexModule(_outer) {
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println("Generated Address Map")
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private val aw = (outer.sharedMemoryTLEdge.bundle.addressBits-1)/4 + 1
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private val fmt = s"\t%${aw}x - %${aw}x %c%c%c%c %s"
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class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle[L]](_outer: L, _io: () => B) extends BareCoreplexModule(_outer, _io)
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with CoreplexNetworkModule
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with BankedL2CoherenceManagersModule
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private def collect(path: List[String], value: ResourceValue): List[(String, ResourceAddress)] = {
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value match {
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case r: ResourceAddress => List((path(1), r))
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case b: ResourceMapping => List((path(1), ResourceAddress(b.address, b.permissions)))
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case ResourceMap(value, _) => value.toList.flatMap { case (key, seq) => seq.flatMap(r => collect(key :: path, r)) }
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case _ => Nil
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}
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}
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private val ranges = collect(Nil, outer.bindingTree).groupBy(_._2).toList.flatMap { case (key, seq) =>
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AddressRange.fromSets(key.address).map { r => (r, key.permissions, seq.map(_._1)) }
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}.sortBy(_._1)
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private val json = ranges.map { case (range, ResourcePermissions(r, w, x, c), names) =>
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println(fmt.format(
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range.base,
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range.base+range.size,
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if (r) 'R' else ' ',
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if (w) 'W' else ' ',
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if (x) 'X' else ' ',
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if (c) 'C' else ' ',
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names.mkString(", ")))
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s"""{"base":[${range.base}],"size":[${range.size}],"r":[$r],"w":[$w],"x":[$x],"c":[$c],"names":[${names.map('"'+_+'"').mkString(",")}]}"""
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}
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println("")
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ElaborationArtefacts.add("memmap.json", s"""{"mapping":[${json.mkString(",")}]}""")
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// Confirm that all of memory was described by DTS
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private val dtsRanges = AddressRange.unify(ranges.map(_._1))
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private val allRanges = AddressRange.unify(outer.topManagers.get.flatMap { m => AddressRange.fromSets(m.address) })
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if (dtsRanges != allRanges) {
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println("Address map described by DTS differs from physical implementation:")
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AddressRange.subtract(allRanges, dtsRanges).foreach { case r =>
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println(s"\texists, but undescribed by DTS: ${r}")
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}
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AddressRange.subtract(dtsRanges, allRanges).foreach { case r =>
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println(s"\tdoes not exist, but described by DTS: ${r}")
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}
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println("")
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}
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}
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