diff --git a/src/main/scala/uncore/ahb/Bundles.scala b/src/main/scala/uncore/ahb/Bundles.scala
new file mode 100644
index 00000000..5822ff74
--- /dev/null
+++ b/src/main/scala/uncore/ahb/Bundles.scala
@@ -0,0 +1,35 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import util.GenericParameterizedBundle
+
+abstract class AHBBundleBase(params: AHBBundleParameters) extends GenericParameterizedBundle(params)
+
+// Signal directions are from the master's point-of-view
+class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
+{
+  // Flow control signals from the master
+  val hmastlock = Bool(OUTPUT)
+  val htrans    = UInt(OUTPUT, width = params.transBits)
+  val hsel      = Bool(OUTPUT) // on a master, drive this with true
+  val hready    = Bool(OUTPUT) // on a master, drive this from readyout
+
+  // Payload signals
+  val hwrite    = Bool(OUTPUT)
+  val haddr     = UInt(OUTPUT, width = params.addrBits)
+  val hsize     = UInt(OUTPUT, width = params.sizeBits)
+  val hburst    = UInt(OUTPUT, width = params.burstBits)
+  val hprot     = UInt(OUTPUT, width = params.protBits)
+  val hwdata    = UInt(OUTPUT, width = params.dataBits)
+
+  val hreadyout = Bool(INPUT)
+  val hresp     = Bool(INPUT)
+  val hrdata    = UInt(INPUT, width = params.dataBits)
+}
+
+object AHBBundle
+{
+  def apply(params: AHBBundleParameters) = new AHBBundle(params)
+}
diff --git a/src/main/scala/uncore/ahb/Nodes.scala b/src/main/scala/uncore/ahb/Nodes.scala
new file mode 100644
index 00000000..79776111
--- /dev/null
+++ b/src/main/scala/uncore/ahb/Nodes.scala
@@ -0,0 +1,59 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import chisel3.internal.sourceinfo.SourceInfo
+import config._
+import diplomacy._
+
+object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, AHBEdgeParameters, AHBEdgeParameters, AHBBundle]
+{
+  def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
+  def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
+  def bundleO(eo: Seq[AHBEdgeParameters]): Vec[AHBBundle] = {
+    require (!eo.isEmpty)
+    Vec(eo.size, AHBBundle(eo.map(_.bundle).reduce(_.union(_))))
+  }
+  def bundleI(ei: Seq[AHBEdgeParameters]): Vec[AHBBundle] = {
+    require (!ei.isEmpty)
+    Vec(ei.size, AHBBundle(ei.map(_.bundle).reduce(_.union(_))))
+  }
+
+  def colour = "#00ccff" // bluish
+  override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString
+  override def labelO(eo: AHBEdgeParameters) = (eo.slave.beatBytes * 8).toString
+
+  def connect(bo: => AHBBundle, bi: => AHBBundle, ei: => AHBEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
+    (None, () => { bi <> bo })
+  }
+
+  override def mixO(pd: AHBMasterPortParameters, node: OutwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]): AHBMasterPortParameters  =
+   pd.copy(masters = pd.masters.map  { c => c.copy (nodePath = node +: c.nodePath) })
+  override def mixI(pu: AHBSlavePortParameters, node: InwardNode[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]): AHBSlavePortParameters =
+   pu.copy(slaves  = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
+}
+
+// Nodes implemented inside modules
+case class AHBIdentityNode() extends IdentityNode(AHBImp)
+case class AHBMasterNode(portParams: AHBMasterPortParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SourceNode(AHBImp)(portParams, numPorts)
+case class AHBSlaveNode(portParams: AHBSlavePortParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SinkNode(AHBImp)(portParams, numPorts)
+case class AHBAdapterNode(
+  masterFn:       Seq[AHBMasterPortParameters]  => AHBMasterPortParameters,
+  slaveFn:        Seq[AHBSlavePortParameters] => AHBSlavePortParameters,
+  numMasterPorts: Range.Inclusive = 1 to 1,
+  numSlavePorts:  Range.Inclusive = 1 to 1)
+  extends InteriorNode(AHBImp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
+
+// Nodes passed from an inner module
+case class AHBOutputNode() extends OutputNode(AHBImp)
+case class AHBInputNode() extends InputNode(AHBImp)
+
+// Nodes used for external ports
+case class AHBBlindOutputNode(portParams: AHBSlavePortParameters) extends BlindOutputNode(AHBImp)(portParams)
+case class AHBBlindInputNode(portParams: AHBMasterPortParameters) extends BlindInputNode(AHBImp)(portParams)
+
+case class AHBInternalOutputNode(portParams: AHBSlavePortParameters) extends InternalOutputNode(AHBImp)(portParams)
+case class AHBInternalInputNode(portParams: AHBMasterPortParameters) extends InternalInputNode(AHBImp)(portParams)
diff --git a/src/main/scala/uncore/ahb/Parameters.scala b/src/main/scala/uncore/ahb/Parameters.scala
new file mode 100644
index 00000000..1af5773c
--- /dev/null
+++ b/src/main/scala/uncore/ahb/Parameters.scala
@@ -0,0 +1,99 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import config._
+import diplomacy._
+import scala.math.max
+
+case class AHBSlaveParameters(
+  address:       Seq[AddressSet],
+  regionType:    RegionType.T  = RegionType.GET_EFFECTS,
+  executable:    Boolean       = false, // processor can execute from this memory
+  nodePath:      Seq[BaseNode] = Seq(),
+  supportsWrite: TransferSizes = TransferSizes.none,
+  supportsRead:  TransferSizes = TransferSizes.none)
+{
+  address.foreach { a => require (a.finite) }
+    address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
+
+  val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
+  val maxTransfer = max(supportsWrite.max, supportsRead.max)
+  val maxAddress = address.map(_.max).max
+  val minAlignment = address.map(_.alignment).min
+
+  // The device had better not support a transfer larger than it's alignment
+  require (minAlignment >= maxTransfer)
+}
+
+case class AHBSlavePortParameters(
+  slaves:    Seq[AHBSlaveParameters],
+  beatBytes: Int)
+{
+  require (!slaves.isEmpty)
+  require (isPow2(beatBytes))
+
+  val maxTransfer = slaves.map(_.maxTransfer).max
+  val maxAddress = slaves.map(_.maxAddress).max
+
+  // Check the link is not pointlessly wide
+  require (maxTransfer >= beatBytes)
+  // Check that the link can be implemented in AHB
+  require (maxTransfer <= beatBytes * AHBParameters.maxTransfer)
+
+  lazy val routingMask = AddressDecoder(slaves.map(_.address))
+  def findSafe(address: UInt) = Vec(slaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
+  def findFast(address: UInt) = Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
+
+  // Require disjoint ranges for addresses
+  slaves.combinations(2).foreach { case Seq(x,y) =>
+    x.address.foreach { a => y.address.foreach { b =>
+      require (!a.overlaps(b))
+    } }
+  }
+}
+
+case class AHBMasterParameters(
+  nodePath: Seq[BaseNode] = Seq())
+{
+  val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
+}
+
+case class AHBMasterPortParameters(
+  masters: Seq[AHBMasterParameters])
+
+case class AHBBundleParameters(
+  addrBits: Int,
+  dataBits: Int)
+{
+  require (dataBits >= 8)
+  require (addrBits >= 1)
+  require (isPow2(dataBits))
+
+  // Bring the globals into scope
+  val transBits = AHBParameters.transBits
+  val burstBits = AHBParameters.burstBits
+  val protBits  = AHBParameters.protBits
+  val sizeBits  = AHBParameters.sizeBits
+
+  def union(x: AHBBundleParameters) =
+    AHBBundleParameters(
+      max(addrBits, x.addrBits),
+      max(dataBits, x.dataBits))
+}
+
+object AHBBundleParameters
+{
+  def apply(master: AHBMasterPortParameters, slave: AHBSlavePortParameters) =
+    new AHBBundleParameters(
+      addrBits = log2Up(slave.maxAddress+1),
+      dataBits = slave.beatBytes * 8)
+}
+
+case class AHBEdgeParameters(
+  master: AHBMasterPortParameters,
+  slave:  AHBSlavePortParameters)
+{
+  val bundle = AHBBundleParameters(master, slave)
+}
diff --git a/src/main/scala/uncore/ahb/Protocol.scala b/src/main/scala/uncore/ahb/Protocol.scala
new file mode 100644
index 00000000..4dbd9f78
--- /dev/null
+++ b/src/main/scala/uncore/ahb/Protocol.scala
@@ -0,0 +1,40 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import chisel3.util.{Irrevocable, IrrevocableIO}
+
+object AHBParameters
+{
+  // These are all fixed by the AHB standard:
+  val transBits = 2
+  val burstBits = 3
+  val protBits  = 4
+  val sizeBits  = 3  // 8*2^s
+
+  val TRANS_IDLE   = UInt(0, width = transBits) // No transfer requested, not in a burst
+  val TRANS_BUSY   = UInt(1, width = transBits) // No transfer requested, in a burst
+  val TRANS_NONSEQ = UInt(2, width = transBits) // First (potentially only) request in a burst
+  val TRANS_SEQ    = UInt(3, width = transBits) // Following requests in a burst
+
+  val BURST_SINGLE = UInt(0, width = burstBits) // Single access (no burst)
+  val BURST_INCR   = UInt(1, width = burstBits) // Incrementing burst of arbitrary length, not crossing 1KB
+  val BURST_WRAP4  = UInt(2, width = burstBits) // 4-beat wrapping burst
+  val BURST_INCR4  = UInt(3, width = burstBits) // 4-beat incrementing burst
+  val BURST_WRAP8  = UInt(4, width = burstBits) // 8-beat wrapping burst
+  val BURST_INCR8  = UInt(5, width = burstBits) // 8-beat incrementing burst
+  val BURST_WRAP16 = UInt(6, width = burstBits) // 16-beat wrapping burst
+  val BURST_INCR16 = UInt(7, width = burstBits) // 16-beat incrementing burst
+
+  val maxTransfer = 16
+
+  val RESP_OKAY  = Bool(false)
+  val RESP_ERROR = Bool(true)
+
+  val PROT_DATA        = UInt(1, width = protBits)
+  val PROT_PRIVILEDGED = UInt(2, width = protBits)
+  val PROT_BUFFERABLE  = UInt(4, width = protBits)
+  val PROT_CACHEABLE   = UInt(8, width = protBits)
+  def PROT_DEFAULT = PROT_DATA | PROT_PRIVILEDGED
+}
diff --git a/src/main/scala/uncore/ahb/RegisterRouter.scala b/src/main/scala/uncore/ahb/RegisterRouter.scala
new file mode 100644
index 00000000..dcdd30ba
--- /dev/null
+++ b/src/main/scala/uncore/ahb/RegisterRouter.scala
@@ -0,0 +1,111 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import config._
+import diplomacy._
+import regmapper._
+import scala.math.{min,max}
+
+class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
+  extends AHBSlaveNode(AHBSlavePortParameters(
+    Seq(AHBSlaveParameters(
+      address       = Seq(address),
+      executable    = executable,
+      supportsWrite = TransferSizes(1, beatBytes * AHBParameters.maxTransfer),
+      supportsRead  = TransferSizes(1, beatBytes * AHBParameters.maxTransfer))),
+    beatBytes  = beatBytes))
+{
+  require (address.contiguous)
+
+  // Calling this method causes the matching AHB bundle to be
+  // configured to route all requests to the listed RegFields.
+  def regmap(mapping: RegField.Map*) = {
+    val ahb = bundleIn(0)
+
+    val indexBits = log2Up((address.mask+1)/beatBytes)
+    val params = RegMapperParams(indexBits, beatBytes, 1)
+    val in = Wire(Decoupled(new RegMapperInput(params)))
+    val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
+
+    val d_phase = RegInit(Bool(false))
+    val d_taken = Reg(Bool())
+    val d_read  = Reg(Bool())
+    val d_index = Reg(UInt(width = indexBits))
+    val d_mask  = Reg(UInt(width = beatBytes))
+
+    // Only send the request to the RR once
+    d_taken := d_phase && in.ready
+    in.valid := d_phase && !d_taken
+
+    in.bits.read  := d_read
+    in.bits.index := d_index
+    in.bits.data  := ahb.hwdata
+    in.bits.mask  := d_mask
+    in.bits.extra := UInt(0)
+
+    ahb.hreadyout := !d_phase || out.valid
+    ahb.hresp     := AHBParameters.RESP_OKAY
+    ahb.hrdata    := out.bits.data
+
+    val request = ahb.htrans === AHBParameters.TRANS_NONSEQ || ahb.htrans === AHBParameters.TRANS_SEQ
+    when (ahb.hready && ahb.hsel && request) {
+      assert (!d_phase || in.ready)
+      d_phase := Bool(true)
+      d_taken := Bool(false)
+      d_read  := !ahb.hwrite
+      d_index := ahb.haddr >> log2Ceil(beatBytes)
+      d_mask  := uncore.tilelink2.maskGen(ahb.haddr, ahb.hsize, beatBytes)
+    }
+
+    out.ready := Bool(true)
+    assert (d_phase || !out.valid)
+  }
+}
+
+object AHBRegisterNode
+{
+  def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
+    new AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
+}
+
+// These convenience methods below combine to make it possible to create a AHB
+// register mapped device from a totally abstract register mapped device.
+
+abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
+{
+  val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
+  val intnode = uncore.tilelink2.IntSourceNode(interrupts)
+}
+
+case class AHBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AHBBundle])(implicit val p: Parameters)
+
+class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle
+{
+  implicit val p = arg.p
+  val interrupts = arg.interrupts
+  val in = arg.in
+}
+
+class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleBase(arg)
+
+class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, router: AHBRegisterRouterBase)
+  extends LazyModuleImp(router) with HasRegMap
+{
+  val io = bundleBuilder
+  val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
+  def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
+}
+
+class AHBRegisterRouter[B <: AHBRegBundleBase, M <: LazyModuleImp]
+   (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
+   (bundleBuilder: AHBRegBundleArg => B)
+   (moduleBuilder: (=> B, AHBRegisterRouterBase) => M)(implicit p: Parameters)
+  extends AHBRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
+{
+  require (isPow2(size))
+  // require (size >= 4096) ... not absolutely required, but highly recommended
+
+  lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
+}
diff --git a/src/main/scala/uncore/ahb/SRAM.scala b/src/main/scala/uncore/ahb/SRAM.scala
new file mode 100644
index 00000000..c173c973
--- /dev/null
+++ b/src/main/scala/uncore/ahb/SRAM.scala
@@ -0,0 +1,99 @@
+// See LICENSE.SiFive for license details.
+
+package uncore.ahb
+
+import Chisel._
+import config._
+import diplomacy._
+
+class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
+{
+  val node = AHBSlaveNode(AHBSlavePortParameters(
+    Seq(AHBSlaveParameters(
+      address       = List(address),
+      regionType    = RegionType.UNCACHED,
+      executable    = executable,
+      supportsRead  = TransferSizes(1, beatBytes * AHBParameters.maxTransfer),
+      supportsWrite = TransferSizes(1, beatBytes * AHBParameters.maxTransfer))),
+    beatBytes  = beatBytes))
+
+  // We require the address range to include an entire beat (for the write mask)
+  require ((address.mask & (beatBytes-1)) == beatBytes-1)
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in = node.bundleIn
+    }
+
+    def bigBits(x: BigInt, tail: List[Boolean] = List.empty[Boolean]): List[Boolean] =
+      if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)
+    val mask = bigBits(address.mask >> log2Ceil(beatBytes))
+
+    val in = io.in(0)
+
+    // The mask and address during the address phase
+    val a_access    = in.htrans === AHBParameters.TRANS_NONSEQ || in.htrans === AHBParameters.TRANS_SEQ
+    val a_request   = in.hready && in.hsel && a_access
+    val a_mask      = uncore.tilelink2.maskGen(in.haddr, in.hsize, beatBytes)
+    val a_address   = Cat((mask zip (in.haddr >> log2Ceil(beatBytes)).toBools).filter(_._1).map(_._2).reverse)
+    val a_write     = in.hwrite
+
+    // The data phase signals
+    val d_wdata = Vec.tabulate(beatBytes) { i => in.hwdata(8*(i+1)-1, 8*i) }
+
+    // AHB writes must occur during the data phase; this poses a structural
+    // hazard with reads which must occur during the address phase. To solve
+    // this problem, we delay the writes until there is a free cycle.
+    //
+    // The idea is to record the address information from address phase and
+    // then as soon as possible flush the pending write. This cannot be done
+    // on a cycle when there is an address phase read, but on any other cycle
+    // the write will execute. In the case of reads following a write, the
+    // result must bypass data from the pending write into the read if they
+    // happen to have matching address.
+
+    // Remove this once HoldUnless is in chisel3
+    def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
+
+    // Pending write?
+    val p_valid     = RegInit(Bool(false))
+    val p_address   = Reg(a_address)
+    val p_mask      = Reg(a_mask)
+    val p_latch_d   = Reg(Bool())
+    val p_wdata     = holdUnless(d_wdata, p_latch_d)
+
+    // Use single-ported memory with byte-write enable
+    val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
+
+    // Decide is the SRAM port is used for reading or (potentially) writing
+    val read = a_request && !a_write
+    // In case we choose to stall, we need to hold the read data
+    val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read))
+    // Whenever the port is not needed for reading, execute pending writes
+    when (!read && p_valid) {
+      p_valid := Bool(false)
+      mem.write(p_address, p_wdata, p_mask.toBools)
+    }
+
+    // Record the request for later?
+    p_latch_d := a_request && a_write
+    when (a_request && a_write) {
+      p_valid   := Bool(true)
+      p_address := a_address
+      p_mask    := a_mask
+    }
+
+    // Does the read need to be muxed with the previous write?
+    val a_bypass = a_address === p_address && p_valid
+    val d_bypass = RegEnable(a_bypass, a_request)
+
+    // Mux in data from the pending write
+    val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
+                      map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
+
+    // Finally, the outputs
+    in.hreadyout := LFSR16(Bool(true))(0) // Bool(true)
+    in.hresp     := AHBParameters.RESP_OKAY
+    in.hrdata    := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
+  }
+}
diff --git a/src/main/scala/uncore/ahb/package.scala b/src/main/scala/uncore/ahb/package.scala
new file mode 100644
index 00000000..ed173388
--- /dev/null
+++ b/src/main/scala/uncore/ahb/package.scala
@@ -0,0 +1,11 @@
+// See LICENSE.SiFive for license details.
+
+package uncore
+
+import Chisel._
+import diplomacy._
+
+package object ahb
+{
+  type AHBOutwardNode = OutwardNodeHandle[AHBMasterPortParameters, AHBSlavePortParameters, AHBBundle]
+}