replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests are incoherently passed through a null coherence hub.
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@ -20,7 +20,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
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class ioRocketICache extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioMem
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val mem = new ioTileLink
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}
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// basic direct mapped instruction cache
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@ -75,7 +75,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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// refill counter
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
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when (io.mem.resp_val) {
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when (io.mem.xact_rep.valid) {
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refill_count := refill_count + UFix(1);
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}
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@ -84,7 +84,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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val tag_addr =
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Mux((state === s_refill_wait), r_cpu_req_idx(indexmsb,indexlsb),
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io.cpu.req_idx(indexmsb,indexlsb)).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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val tag_we = (state === s_refill_wait) && io.mem.xact_rep.valid;
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val data_addr =
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count),
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io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix;
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@ -112,10 +112,10 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
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// data array
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val data_array = Mem(sets*REFILL_CYCLES){ io.mem.resp_data }
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val data_array = Mem(sets*REFILL_CYCLES){ io.mem.xact_rep.bits.data }
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data_array.setReadLatency(1);
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data_array.setTarget('inst);
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val data_out = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val && repl_me)
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val data_out = data_array.rw(data_addr, io.mem.xact_rep.bits.data, io.mem.xact_rep.valid && repl_me)
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data_mux.io.sel(i) := hit
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data_mux.io.in(i) := (data_out >> word_shift)(databits-1,0);
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@ -128,10 +128,11 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_hit;
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rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit);
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io.cpu.resp_data := data_mux.io.out
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io.mem.req_val := (state === s_request);
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io.mem.req_rw := Bool(false)
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io.mem.req_addr := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.req_data_val := Bool(false)
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io.mem.xact_init.valid := (state === s_request)
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io.mem.xact_init.bits.t_type := X_READ_UNCACHED
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io.mem.xact_init.bits.has_data := Bool(false)
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io.mem.xact_init.bits.address := r_cpu_miss_addr(tagmsb,indexlsb).toUFix
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io.mem.xact_init_data.valid := Bool(false)
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// control state machine
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switch (state) {
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@ -148,19 +149,19 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
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}
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is (s_request)
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{
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when (io.mem.req_rdy) {
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when (io.mem.xact_init.ready) {
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state := s_refill_wait;
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}
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}
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is (s_refill_wait) {
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when (io.mem.resp_val) {
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when (io.mem.xact_rep.valid) {
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state := s_refill;
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}
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}
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is (s_refill) {
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when (io.mem.resp_val && (~refill_count === UFix(0))) {
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when (io.mem.xact_rep.valid && refill_count.andR) {
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state := s_ready;
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}
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}
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}
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}
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}
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