riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix fpga build

Browse Source
This commit is contained in:
Andrew Waterman 2012-02-23 22:19:11 -08:00
parent 52da831aa3
commit 012028efaa
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/htif.scala
View File

@ -125,7 +125,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
} }
io.mem.req_val := state === state_mem_req io.mem.req_val := state === state_mem_req
io.mem.req_rw := cmd === cmd_writemem io.mem.req_rw := cmd === cmd_writemem
io.mem.req_addr := addr >> UFix(3) io.mem.req_addr := addr >> UFix(OFFSET_BITS-3)
io.mem.req_wdata := mem_req_data io.mem.req_wdata := mem_req_data
pcr_done := Bool(false) pcr_done := Bool(false)