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BusBlocker: rename a variable

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Wesley W. Terpstra 2017-08-08 16:44:51 -07:00
parent 6d6fc38787
commit 010ba94474
1 changed files with 2 additions and 2 deletions
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src/main/scala/devices/tilelink/BusBlocker.scala
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@ -98,8 +98,8 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
// Determine if a request is allowed // Determine if a request is allowed
val needW = in.a.bits.opcode =/= TLMessages.Get val needW = in.a.bits.opcode =/= TLMessages.Get
val needR = in.a.bits.opcode =/= TLMessages.PutFullData && in.a.bits.opcode =/= TLMessages.PutPartialData val needR = in.a.bits.opcode =/= TLMessages.PutFullData && in.a.bits.opcode =/= TLMessages.PutPartialData
val lte = Bool(false) +: pmps.map(in.a.bits.address < _.address) val lt = Bool(false) +: pmps.map(in.a.bits.address < _.address)
val sel = (pmps.map(_.a) zip (lte.init zip lte.tail)) map { case (a, (l, r)) => a(0) && !l && r } val sel = (pmps.map(_.a) zip (lt.init zip lt.tail)) map { case (a, (l, r)) => a(0) && !l && r }
val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW)) val ok = pmps.map(p => (p.r(0) || !needR) && (p.w(0) || !needW))
val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(false)) // no match => deny val allow = PriorityMux(sel :+ Bool(true), ok :+ Bool(false)) // no match => deny