riscv/rocket-chip
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use the parameters used to create the original object

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Henry Cook
2015-08-10 14:35:08 -07:00
parent 01fc61ba96
commit 005752e2a6
1 changed files with 2 additions and 2 deletions
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4
uncore/src/main/scala/uncore.scala
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@@ -12,12 +12,12 @@ trait CoherenceAgentParameters extends UsesParameters {
val nReleaseTransactors = 1 val nReleaseTransactors = 1
val nAcquireTransactors = params(NAcquireTransactors) val nAcquireTransactors = params(NAcquireTransactors)
val nTransactors = nReleaseTransactors + nAcquireTransactors val nTransactors = nReleaseTransactors + nAcquireTransactors
def outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)}) val outerTLParams = params.alterPartial({ case TLId => params(OuterTLId)})
val outerDataBeats = outerTLParams(TLDataBeats) val outerDataBeats = outerTLParams(TLDataBeats)
val outerDataBits = outerTLParams(TLDataBits) val outerDataBits = outerTLParams(TLDataBits)
val outerBeatAddrBits = log2Up(outerDataBeats) val outerBeatAddrBits = log2Up(outerDataBeats)
val outerByteAddrBits = log2Up(outerDataBits/8) val outerByteAddrBits = log2Up(outerDataBits/8)
def innerTLParams = params.alterPartial({case TLId => params(InnerTLId)}) val innerTLParams = params.alterPartial({case TLId => params(InnerTLId)})
val innerDataBeats = innerTLParams(TLDataBeats) val innerDataBeats = innerTLParams(TLDataBeats)
val innerDataBits = innerTLParams(TLDataBits) val innerDataBits = innerTLParams(TLDataBits)
val innerBeatAddrBits = log2Up(innerDataBeats) val innerBeatAddrBits = log2Up(innerDataBeats)