diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala
index 28cb5217..29eba5da 100644
--- a/uncore/src/main/scala/htif.scala
+++ b/uncore/src/main/scala/htif.scala
@@ -91,7 +91,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
 
   val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(UInt(), 6)
 
-  val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.needWidth()-1, 0)
+  val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.getWidth-1, 0)
   val pcr_coreid = addr(log2Up(nTiles)-1+20+1,20)
   val pcr_wdata = packet_ram(0)
 
diff --git a/uncore/src/main/scala/llc.scala b/uncore/src/main/scala/llc.scala
index 1c8671d0..3a21cdca 100644
--- a/uncore/src/main/scala/llc.scala
+++ b/uncore/src/main/scala/llc.scala
@@ -15,8 +15,8 @@ class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UIn
     val rdata = gen.asOutput
   }
   val data = gen
-  val colMux = if (2*data.needWidth() <= leaf.data.needWidth() && n > leaf.n) 1 << math.floor(math.log(leaf.data.needWidth()/data.needWidth())/math.log(2)).toInt else 1
-  val nWide = if (data.needWidth() > leaf.data.needWidth()) 1+(data.needWidth()-1)/leaf.data.needWidth() else 1
+  val colMux = if (2*data.getWidth <= leaf.data.getWidth && n > leaf.n) 1 << math.floor(math.log(leaf.data.getWidth/data.getWidth)/math.log(2)).toInt else 1
+  val nWide = if (data.getWidth > leaf.data.getWidth) 1+(data.getWidth-1)/leaf.data.getWidth else 1
   val nDeep = if (n > colMux*leaf.n) 1+(n-1)/(colMux*leaf.n) else 1
   if (nDeep > 1 || colMux > 1)
     require(isPow2(n) && isPow2(leaf.n))
@@ -39,10 +39,10 @@ class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UIn
       var dout: Bits = null
       val ridx = if (postLatency > 0) Reg(Bits()) else null
 
-      var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.needWidth()*(j+1))-1, leaf.data.needWidth()*j))
+      var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
       if (colMux > 1)
-        wmask0 = wmask0 & FillInterleaved(gen.needWidth(), UIntToOH(in.bits.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
-      val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.needWidth()*(j+1))-1, leaf.data.needWidth()*j))
+        wmask0 = wmask0 & FillInterleaved(gen.getWidth, UIntToOH(in.bits.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
+      val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
       when (in.valid) {
         when (in.bits.rw) { mem.write(idx, wdata0, wmask0) }
         .otherwise { if (postLatency > 0) ridx := idx }
@@ -61,7 +61,7 @@ class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UIn
 
     var colMuxOut = rdataWide
     if (colMux > 1) {
-      val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.needWidth()*(k+1)-1, gen.needWidth()*k)))
+      val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.getWidth*(k+1)-1, gen.getWidth*k)))
       colMuxOut = colMuxIn(r.bits(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
     }
 
@@ -268,7 +268,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, refill_cycles: Int, leaf: Mem[
   data.io.in.bits.addr := Cat(io.req.bits.way, io.req.bits.addr(log2Up(sets)-1, 0), count).toUInt
   data.io.in.bits.rw := io.req.bits.rw
   data.io.in.bits.wdata := io.req_data.bits.data
-  data.io.in.bits.wmask := SInt(-1, io.req_data.bits.data.needWidth())
+  data.io.in.bits.wmask := SInt(-1, io.req_data.bits.data.getWidth)
   when (valid) {
     data.io.in.valid := Mux(req.rw, io.req_data.valid, qReady)
     data.io.in.bits.addr := Cat(req.way, req.addr(log2Up(sets)-1, 0), count).toUInt
@@ -385,7 +385,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int, ta
     for (i <- 0 until ways)
       s2_tags(i) := tags.io.rdata(metaWidth*(i+1)-1, metaWidth*i)
   }
-  val s2_hits = s2_tags.map(t => t(tagWidth) && s2.addr(s2.addr.needWidth()-1, s2.addr.needWidth()-tagWidth) === t(tagWidth-1, 0))
+  val s2_hits = s2_tags.map(t => t(tagWidth) && s2.addr(s2.addr.getWidth-1, s2.addr.getWidth-tagWidth) === t(tagWidth-1, 0))
   val s2_hit_way = OHToUInt(s2_hits)
   val s2_hit = s2_hits.reduceLeft(_||_)
   val s2_hit_dirty = s2_tags(s2_hit_way)(tagWidth+1)
@@ -395,7 +395,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int, ta
 
   val tag_we = initialize || setDirty || mshr.io.tag.fire()
   val tag_waddr = Mux(initialize, initCount, Mux(setDirty, s2.addr, mshr.io.tag.bits.addr))
-  val tag_wdata = Cat(setDirty, !initialize, Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.needWidth()-1, mshr.io.tag.bits.addr.needWidth()-tagWidth))
+  val tag_wdata = Cat(setDirty, !initialize, Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.getWidth-1, mshr.io.tag.bits.addr.getWidth-tagWidth))
   val tag_wmask = Mux(initialize, SInt(-1, ways), UIntToOH(Mux(setDirty, s2_hit_way, mshr.io.tag.bits.way)))
   tags.io.in.valid := io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy || tag_we
   tags.io.in.bits.addr := Mux(tag_we, tag_waddr, Mux(replay_s2, s2.addr, io.cpu.req_cmd.bits.addr)(log2Up(sets)-1,0))