2017-03-27 12:29:07 +02:00
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// See LICENSE.SiFive for license details.
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2017-07-07 19:48:16 +02:00
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package freechips.rocketchip.util
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2017-03-27 12:29:07 +02:00
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import Chisel._
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/** Reset: asynchronous assert,
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* synchronous de-assert
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*
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*/
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class ResetCatchAndSync (sync: Int = 3) extends Module {
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2017-09-13 01:05:13 +02:00
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override def desiredName = s"ResetCatchAndSync_d${sync}"
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2017-03-27 12:29:07 +02:00
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val io = new Bundle {
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val sync_reset = Bool(OUTPUT)
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2017-09-13 01:05:13 +02:00
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val psd_test_reset = Bool(INPUT)
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val psd_test_mode = Bool(INPUT)
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2017-03-27 12:29:07 +02:00
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}
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2017-09-13 01:05:13 +02:00
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io.sync_reset := Mux(io.psd_test_mode, io.psd_test_reset,
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~AsyncResetSynchronizerShiftReg(Bool(true), sync))
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2017-03-27 12:29:07 +02:00
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}
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object ResetCatchAndSync {
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2017-09-13 01:05:13 +02:00
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
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psd_test_mode: Bool = Bool(false), psd_test_reset: Bool = Bool(false)): Bool = {
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2017-03-27 12:29:07 +02:00
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.clock := clk
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catcher.reset := rst
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2017-09-13 01:05:13 +02:00
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catcher.io.psd_test_mode := psd_test_mode
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catcher.io.psd_test_reset:= psd_test_reset
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2017-03-27 12:29:07 +02:00
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catcher.io.sync_reset
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}
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def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
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def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
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2017-09-13 01:05:13 +02:00
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def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, sync, Some(name),
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psd_test_mode, psd_test_reset)
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def apply(clk: Clock, rst: Bool, name: String, psd_test_mode: Bool, psd_test_reset: Bool): Bool = apply(clk, rst, name = Some(name),
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psd_test_mode = psd_test_mode, psd_test_reset = psd_test_reset)
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2017-03-27 12:29:07 +02:00
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}
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