2012-02-09 10:28:16 +01:00
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package Top
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import Chisel._
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import Node._
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import Constants._
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import Instructions._
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import hwacha._
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class ioDpathVec extends Bundle
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{
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val valid = Bool(INPUT)
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val sr_ev = Bool(INPUT)
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val inst = Bits(32, INPUT)
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val waddr = UFix(5, INPUT)
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val raddr1 = UFix(5, INPUT)
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val vecbank = Bits(8, INPUT)
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val vecbankcnt = UFix(4, INPUT)
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val wdata = Bits(64, INPUT)
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val rs2 = Bits(64, INPUT)
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2012-02-09 11:35:09 +01:00
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val wen = Bool(OUTPUT)
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2012-02-09 10:28:16 +01:00
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val appvl = UFix(12, OUTPUT)
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val vcmdq = new io_vec_cmdq()
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val vximm1q = new io_vec_ximm1q()
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val vximm2q = new io_vec_ximm2q()
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}
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class rocketDpathVec extends Component
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{
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val io = new ioDpathVec()
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val veccs =
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ListLookup(io.inst,
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// appvlmask
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// | vcmdq
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// wen | | vximm1q
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// val vcmd vimm | fn | | | vximm2q
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// | | | | | | | | |
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List(N,VCMD_X, VIMM_X, N,VEC_X ,N,N,N,N),Array(
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VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,Y,VEC_CFG,N,Y,Y,N),
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VSETVL-> List(Y,VCMD_I, VIMM_VLEN,Y,VEC_VL ,N,Y,Y,N),
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VF-> List(Y,VCMD_I, VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VMVV-> List(Y,VCMD_TX,VIMM_X, N,VEC_X ,Y,Y,N,N),
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VMSV-> List(Y,VCMD_TX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VFMVV-> List(Y,VCMD_TF,VIMM_X, N,VEC_X ,Y,Y,N,N),
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FENCE_L_V-> List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
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FENCE_G_V-> List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
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FENCE_L_CV->List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
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FENCE_G_CV->List(Y,VCMD_F, VIMM_X, N,VEC_X ,N,Y,N,N),
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VLD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLWU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLHU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLBU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VSD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VSW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VSH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VSB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VFLD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VFLW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VFSD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VFSW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,N),
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VLSTD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VSSTD-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VSSTW-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VSSTH-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VSSTB-> List(Y,VCMD_MX,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y),
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VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, N,VEC_X ,Y,Y,Y,Y)
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))
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val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs
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val wb_vec_cmdq_val :: wb_vec_ximm1q_val :: wb_vec_ximm2q_val :: Nil = veccs0
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2012-02-09 11:35:09 +01:00
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val nxregs = Cat(UFix(0,1),io.inst(15,10).toUFix) // FIXME: to make the nregs width 7 bits
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val nfregs = io.inst(21,16).toUFix
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val nregs = nxregs + nfregs
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2012-02-09 10:28:16 +01:00
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val uts_per_bank = MuxLookup(
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nregs, UFix(4,9), Array(
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UFix(0,7) -> UFix(256,9),
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UFix(1,7) -> UFix(256,9),
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UFix(2,7) -> UFix(256,9),
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UFix(3,7) -> UFix(128,9),
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UFix(4,7) -> UFix(85,9),
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UFix(5,7) -> UFix(64,9),
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UFix(6,7) -> UFix(51,9),
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UFix(7,7) -> UFix(42,9),
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UFix(8,7) -> UFix(36,9),
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UFix(9,7) -> UFix(32,9),
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UFix(10,7) -> UFix(28,9),
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UFix(11,7) -> UFix(25,9),
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UFix(12,7) -> UFix(23,9),
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UFix(13,7) -> UFix(21,9),
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UFix(14,7) -> UFix(19,9),
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UFix(15,7) -> UFix(18,9),
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UFix(16,7) -> UFix(17,9),
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UFix(17,7) -> UFix(16,9),
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UFix(18,7) -> UFix(15,9),
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UFix(19,7) -> UFix(14,9),
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UFix(20,7) -> UFix(13,9),
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UFix(21,7) -> UFix(12,9),
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UFix(22,7) -> UFix(12,9),
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UFix(23,7) -> UFix(11,9),
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UFix(24,7) -> UFix(11,9),
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UFix(25,7) -> UFix(10,9),
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UFix(26,7) -> UFix(10,9),
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UFix(27,7) -> UFix(9,9),
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UFix(28,7) -> UFix(9,9),
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UFix(29,7) -> UFix(9,9),
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UFix(30,7) -> UFix(8,9),
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UFix(31,7) -> UFix(8,9),
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UFix(32,7) -> UFix(8,9),
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UFix(33,7) -> UFix(8,9),
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UFix(34,7) -> UFix(7,9),
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UFix(35,7) -> UFix(7,9),
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UFix(36,7) -> UFix(7,9),
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UFix(37,7) -> UFix(7,9),
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UFix(38,7) -> UFix(6,9),
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UFix(39,7) -> UFix(6,9),
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UFix(40,7) -> UFix(6,9),
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UFix(41,7) -> UFix(6,9),
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UFix(42,7) -> UFix(6,9),
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UFix(43,7) -> UFix(6,9),
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UFix(44,7) -> UFix(5,9),
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UFix(45,7) -> UFix(5,9),
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UFix(46,7) -> UFix(5,9),
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UFix(47,7) -> UFix(5,9),
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UFix(48,7) -> UFix(5,9),
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UFix(49,7) -> UFix(5,9),
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UFix(50,7) -> UFix(5,9),
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UFix(51,7) -> UFix(5,9),
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UFix(52,7) -> UFix(5,9)
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))
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val reg_hwvl = Reg(resetVal = UFix(32, 12))
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val reg_appvl0 = Reg(resetVal = Bool(true))
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val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)
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val hwvl = Mux(wb_vec_fn.toBool, hwvl_vcfg, reg_hwvl)
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val appvl = Mux(io.wdata(11,0) < hwvl, io.wdata(11,0), hwvl).toUFix
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when (io.valid && wb_vec_wen.toBool && wb_vec_fn.toBool)
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{
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reg_hwvl <== hwvl_vcfg
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reg_appvl0 <== !(appvl.orR())
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}
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2012-02-09 11:35:09 +01:00
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io.wen := io.valid && wb_vec_wen.toBool
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2012-02-09 10:28:16 +01:00
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io.appvl := appvl
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val vlenm1 = appvl - Bits(1,1)
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val valid_common = io.valid && io.sr_ev && wb_vec_val.toBool && !(wb_vec_appvlmask.toBool && reg_appvl0)
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io.vcmdq.valid := valid_common && wb_vec_cmdq_val
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io.vximm1q.valid := valid_common && wb_vec_ximm1q_val
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io.vximm2q.valid := valid_common && wb_vec_ximm2q_val
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io.vcmdq.bits :=
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Mux(wb_sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
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Mux(wb_sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)),
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Mux(wb_sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1),
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Mux(wb_sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), io.waddr, Bits(1,1), io.raddr1),
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Mux(wb_sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), io.waddr, Bits(0,1), io.waddr),
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Mux(wb_sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), io.waddr, Bits(1,1), io.waddr),
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Bits(0,20)))))))
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io.vximm1q.bits :=
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Mux(wb_sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1),
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io.wdata) // VIMM_ALU
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io.vximm2q.bits := io.rs2
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}
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