23 lines
570 B
Scala
23 lines
570 B
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.system
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.LazyModule
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class TestHarness()(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val dut = Module(LazyModule(new ExampleRocketSystem).module)
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dut.reset := reset | dut.debug.ndreset
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dut.tieOffInterrupts()
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dut.connectSimAXIMem()
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dut.connectSimAXIMMIO()
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dut.tieOffAXI4SlavePort()
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dut.connectDebug(clock, reset, io.success)
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}
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