rocket-chip/.travis.yml

git:
  submodules: false
language: scala
# run on new infrastructure
sudo: false
cache:
  apt: true
  directories:
    $HOME/.ivy2
    regression/install
    emulator/verilator

# packages needed to build riscv-tools
addons:
  apt:
    sources:
      - ubuntu-toolchain-r-test
    packages:
      - gcc-4.8
      - g++-4.8
      - gperf
      - autoconf
      - automake
      - autotools-dev
      - libmpc-dev
      - libmpfr-dev
      - libgmp-dev
      - gawk
      - build-essential
      - bison
      - flex
      - texinfo

env:
  matrix:
    - SUITE=RocketSuiteA
    - SUITE=RocketSuiteB
    - SUITE=RocketSuiteC
    - SUITE=GroundtestSuite
    - SUITE=UnittestSuite

# blacklist private branches
branches:
  except:
    - hwacha
    - boom
    - /^hurricane.*$/

before_install:
  - export CXX=g++-4.8 CC=gcc-4.8

script:
  - make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default
  - make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default

before_cache:
  - ls -t regression/install | tail -n+2 | sed s@^@regression/install/@ | xargs rm -rf
Don't allow travis to recurse through submodules 2016-05-25 20:21:06 +02:00			`git:`
			`submodules: false`
add travis support and tests 2015-08-25 22:29:20 +02:00			`language: scala`
			`# run on new infrastructure`
			`sudo: false`
Enable travis caching 2016-02-23 02:41:01 +01:00			`cache:`
			`apt: true`
			`directories:`
			`$HOME/.ivy2`
			`regression/install`
have Travis cache the entire verilator directory 2016-09-05 00:05:30 +02:00			`emulator/verilator`
format .travis.yml (trigger rebuilt to test cache) 2016-02-23 17:44:15 +01:00
add travis support and tests 2015-08-25 22:29:20 +02:00			`# packages needed to build riscv-tools`
			`addons:`
			`apt:`
			`sources:`
			`- ubuntu-toolchain-r-test`
			`packages:`
			`- gcc-4.8`
			`- g++-4.8`
			`- gperf`
			`- autoconf`
			`- automake`
			`- autotools-dev`
			`- libmpc-dev`
			`- libmpfr-dev`
			`- libgmp-dev`
			`- gawk`
			`- build-essential`
			`- bison`
			`- flex`
			`- texinfo`

			`env:`
[travis] add multiple configs including rocc 2015-11-28 16:17:49 +01:00			`matrix:`
travis: split RocketSuite into three smaller tests suites 2016-11-22 00:12:05 +01:00			`- SUITE=RocketSuiteA`
			`- SUITE=RocketSuiteB`
			`- SUITE=RocketSuiteC`
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations. 2016-08-16 07:03:03 +02:00			`- SUITE=GroundtestSuite`
refactor unittest framework as a result, there's another SUITE that needs to run 2016-09-15 03:10:21 +02:00			`- SUITE=UnittestSuite`
add travis support and tests 2015-08-25 22:29:20 +02:00
blacklist private branches from travis 2015-09-09 00:13:38 +02:00			`# blacklist private branches`
			`branches:`
			`except:`
			`- hwacha`
			`- boom`
Don't build any hurricane branches Don't mean to eat up travis bandwidth but shared branches sometimes get made. 2016-10-15 01:38:10 +02:00			`- /^hurricane.*$/`
blacklist private branches from travis 2015-09-09 00:13:38 +02:00
add travis support and tests 2015-08-25 22:29:20 +02:00			`before_install:`
			`- export CXX=g++-4.8 CC=gcc-4.8`

			`script:`
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations. 2016-08-16 07:03:03 +02:00			`- make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default`
			`- make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default`
Move travis to the regression Makefile We want to add support for caching riscv-tools builds on Travis and the easiest way to do so looks like to jus go ahead and use 2016-02-23 02:29:07 +01:00
			`before_cache:`
travis: delete oldest caches; not newest 2016-11-22 01:51:52 +01:00			`- ls -t regression/install \| tail -n+2 \| sed s@^@regression/install/@ \| xargs rm -rf`