85 lines
1.7 KiB
Scala
85 lines
1.7 KiB
Scala
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package uncore.util
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import Chisel._
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import cde.{Parameters}
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import junctions.{ParameterizedBundle}
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/** This black-boxes an Async Reset
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* Reg.
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*
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* Because Chisel doesn't support
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* parameterized black boxes,
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* we unfortunately have to
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* instantiate a number of these.
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*
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* Do not confuse an asynchronous
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* reset signal with an asynchronously
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* reset reg. You should still
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* properly synchronize your reset
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* deassertion.
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*
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* @param d Data input
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* @param q Data Output
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* @param clk Clock Input
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* @param rst Reset Input
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*
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* @param init Value to write at Reset.
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* This is a constant,
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* but this construction
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* will likely make backend flows
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* and lint tools unhappy.
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*
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*/
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class AsyncResetReg extends BlackBox {
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val io = new Bundle {
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val d = Bool(INPUT)
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val q = Bool(OUTPUT)
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val clk = Clock(INPUT)
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val rst = Bool(INPUT)
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val init = Bool(INPUT)
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}
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}
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class SimpleRegIO(val w: Int)(implicit val p: Parameters) extends ParameterizedBundle()(p){
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val d = UInt(INPUT, width = w)
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val q = UInt(OUTPUT, width = w)
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val en = Bool(INPUT)
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}
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class AsyncResetRegVec(val w: Int, val init: Int)(implicit val p: Parameters) extends Module {
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val io = new SimpleRegIO(w)(p)
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val bb_q = Wire(UInt(width = w))
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val bb_d = Wire(UInt(width = w))
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val init_val = Wire(UInt(width = w))
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init_val := UInt(init, width = w)
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val async_regs = List.fill(w)(Module (new AsyncResetReg))
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bb_q := (async_regs.map(_.io.q)).asUInt()
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bb_d := Mux(io.en , io.d , bb_q)
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io.q := bb_q
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for ((reg, idx) <- async_regs.zipWithIndex) {
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reg.io.clk := clock
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reg.io.rst := reset
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reg.io.init := init_val(idx)
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reg.io.d := bb_d(idx)
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}
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}
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