381 lines
16 KiB
Scala
381 lines
16 KiB
Scala
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// See LICENSE for license details.
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package uncore
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import Chisel._
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case object L2StoreDataQueueDepth extends Field[Int]
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trait BroadcastHubParameters extends CoherenceAgentParameters {
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val sdqDepth = params(L2StoreDataQueueDepth)*innerDataBeats
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val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(sdqDepth))
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val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases
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}
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class DataQueueLocation extends Bundle with BroadcastHubParameters {
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val idx = UInt(width = dqIdxBits)
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val loc = UInt(width = log2Ceil(nDataQueueLocations))
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}
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object DataQueueLocation {
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def apply(idx: UInt, loc: UInt) = {
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val d = new DataQueueLocation
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d.idx := idx
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d.loc := loc
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d
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}
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}
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class L2BroadcastHub(bankId: Int) extends ManagerCoherenceAgent
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with BroadcastHubParameters {
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val internalDataBits = new DataQueueLocation().getWidth
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val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
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// Create SHRs for outstanding transactions
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val trackerList = (0 until nReleaseTransactors).map(id =>
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Module(new BroadcastVoluntaryReleaseTracker(id, bankId), {case TLDataBits => internalDataBits})) ++
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(nReleaseTransactors until nTransactors).map(id =>
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Module(new BroadcastAcquireTracker(id, bankId), {case TLDataBits => internalDataBits}))
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// Propagate incoherence flags
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trackerList.map(_.io.incoherent := io.incoherent.toBits)
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// Queue to store impending Put data
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val acquire = io.inner.acquire
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = acquire.fire() && acquire.bits.payload.hasData()
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val sdq = Vec.fill(sdqDepth){ Reg(io.inner.acquire.bits.payload.data) }
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when (sdq_enq) { sdq(sdq_alloc_id) := acquire.bits.payload.data }
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// Handle acquire transaction initiation
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.bits.payload.data := DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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t.acquire.valid := alloc_arb.io.in(i).ready
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}
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && sdq_rdy && !block_acquires
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alloc_arb.io.out.ready := acquire.valid && sdq_rdy && !block_acquires
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// Queue to store impending Voluntary Release data
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val release = io.inner.release
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val voluntary = release.bits.payload.isVoluntary()
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val vwbdq_enq = release.fire() && voluntary && release.bits.payload.hasData()
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val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
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val vwbdq = Vec.fill(innerDataBeats){ Reg(release.bits.payload.data) } //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := release.bits.payload.data }
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// Handle releases, which might be voluntary and might have data
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val release_idx = Vec(trackerList.map(_.io.has_release_match)).indexWhere{b: Bool => b}
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.inner
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t.release.bits := release.bits
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t.release.bits.payload.data := (if (i < nReleaseTransactors)
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DataQueueLocation(rel_data_cnt, inVolWBQueue)
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else DataQueueLocation(UInt(0), inClientReleaseQueue)).toBits
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t.release.valid := release.valid && (release_idx === UInt(i))
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}
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx)
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// Wire finished transaction acks
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val ack = io.inner.finish
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trackerList.map(_.io.inner.finish.valid := ack.valid)
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trackerList.map(_.io.inner.finish.bits := ack.bits)
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ack.ready := Bool(true)
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// Wire probe requests and grant reply to clients, finish acks from clients
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// Note that we bypass the Grant data subbundles
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io.inner.grant.bits.payload.data := io.outer.grant.bits.payload.data
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io.inner.grant.bits.payload.addr_beat := io.outer.grant.bits.payload.addr_beat
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
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// Create an arbiter for the one memory port
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
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{ case TLId => params(OuterTLId)
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case TLDataBits => internalDataBits })
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
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// Get the pending data out of the store data queue
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val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.payload.data)
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val is_in_sdq = outer_data_ptr.loc === inStoreQueue
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val free_sdq = io.outer.acquire.fire() &&
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io.outer.acquire.bits.payload.hasData() &&
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outer_data_ptr.loc === inStoreQueue
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io.outer.acquire.bits.payload.data := MuxLookup(outer_data_ptr.loc, release.bits.payload.data, Array(
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inStoreQueue -> sdq(outer_data_ptr.idx),
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inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
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io.outer <> outer_arb.io.out
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// Update SDQ valid bits
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when (io.outer.acquire.valid || sdq_enq) {
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sdq_val := sdq_val & ~(UIntToOH(outer_data_ptr.idx) & Fill(sdqDepth, free_sdq)) |
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PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq)
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}
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}
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class BroadcastXactTracker extends XactTracker {
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val io = new ManagerXactTrackerIO
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}
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class BroadcastVoluntaryReleaseTracker(trackerId: Int, bankId: Int) extends BroadcastXactTracker {
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val s_idle :: s_outer :: s_grant :: s_ack :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_idle)
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val xact_src = Reg(io.inner.release.bits.header.src.clone)
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val xact = Reg(Bundle(new Release, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Vec.fill(innerDataBeats){ Reg(io.irel().data.clone) }
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val coh = ManagerMetadata.onReset
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val collect_irel_data = Reg(init=Bool(false))
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val irel_data_valid = Reg(init=Bits(0, width = innerDataBeats))
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val (oacq_data_cnt, oacq_data_done) = connectOutgoingDataBeatCounter(io.outer.acquire)
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io.has_acquire_conflict := Bool(false)
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io.has_release_match := io.irel().isVoluntary()
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io.has_acquire_match := Bool(false)
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io.outer.acquire.valid := Bool(false)
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io.outer.grant.ready := Bool(false)
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io.outer.finish.valid := Bool(false)
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io.inner.acquire.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.grant.valid := Bool(false)
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io.inner.finish.ready := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := xact_src
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io.inner.grant.bits.payload := coh.makeGrant(xact, UInt(trackerId))
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//TODO: Use io.outer.release instead?
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io.outer.acquire.bits.payload := Bundle(PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = oacq_data_cnt,
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data = data_buffer(oacq_data_cnt)))(outerTLParams)
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when(collect_irel_data) {
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io.inner.release.ready := Bool(true)
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when(io.inner.release.valid) {
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data_buffer(io.irel().addr_beat) := io.irel().data
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irel_data_valid(io.irel().addr_beat) := Bool(true)
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}
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when(irel_data_done) { collect_irel_data := Bool(false) }
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}
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switch (state) {
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is(s_idle) {
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io.inner.release.ready := Bool(true)
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when( io.inner.release.valid ) {
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xact_src := io.inner.release.bits.header.src
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xact := io.irel()
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data_buffer(UInt(0)) := io.irel().data
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collect_irel_data := io.irel().hasMultibeatData()
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irel_data_valid := io.irel().hasData() << io.irel().addr_beat
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state := Mux(io.irel().hasData(), s_outer,
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Mux(io.irel().requiresAck(), s_ack, s_idle))
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}
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}
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is(s_outer) {
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io.outer.acquire.valid := !collect_irel_data || irel_data_valid(oacq_data_cnt)
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when(oacq_data_done) {
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state := Mux(xact.requiresAck(), s_grant, s_idle)
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}
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}
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is(s_grant) { // Forward the Grant.voluntaryAck
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io.outer.grant.ready := io.inner.grant.ready
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io.inner.grant.valid := io.outer.grant.valid
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when(io.inner.grant.fire()) {
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state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
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}
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}
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is(s_ack) {
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// TODO: This state is unnecessary if no client will ever issue the
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// pending Acquire that caused this writeback until it receives the
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// Grant.voluntaryAck for this writeback
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io.inner.finish.ready := Bool(true)
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when(io.inner.finish.valid) { state := s_idle }
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}
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}
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}
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class BroadcastAcquireTracker(trackerId: Int, bankId: Int) extends BroadcastXactTracker {
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7)
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val state = Reg(init=s_idle)
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val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
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val xact = Reg(Bundle(new Acquire, { case TLId => params(InnerTLId); case TLDataBits => 0 }))
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val data_buffer = Vec.fill(innerDataBeats){ Reg(io.iacq().data.clone) }
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val coh = ManagerMetadata.onReset
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assert(!(state != s_idle && xact.isBuiltInType() &&
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Vec(Acquire.getType, Acquire.putType, Acquire.putAtomicType).contains(xact.a_type)),
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"Broadcast Hub does not support PutAtomics or subblock Gets/Puts") // TODO
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val release_count = Reg(init=UInt(0, width = log2Up(nClients)))
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val probe_flags = Reg(init=Bits(0, width = nClients))
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val curr_p_id = PriorityEncoder(probe_flags)
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val probe_initial_flags = Bits(width = nClients)
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probe_initial_flags := Bits(0)
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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val probe_self = io.inner.acquire.bits.payload.requiresSelfProbe()
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val myflag = Mux(probe_self, Bits(0),
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UIntToOH(io.inner.acquire.bits.header.src(log2Up(nClients)-1,0)))
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probe_initial_flags := ~(io.incoherent.toBits | myflag)
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val collect_iacq_data = Reg(init=Bool(false))
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val iacq_data_valid = Reg(init=Bits(0, width = innerDataBeats))
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val iacq_data_done = connectIncomingDataBeatCounter(io.inner.acquire)
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val (ignt_data_cnt, ignt_data_done) = connectOutgoingDataBeatCounter(io.inner.grant)
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val (oacq_data_cnt, oacq_data_done) = connectOutgoingDataBeatCounter(io.outer.acquire)
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val ognt_data_done = connectIncomingDataBeatCounter(io.outer.grant)
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val pending_ognt_ack = Reg(init=Bool(false))
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val pending_outer_write = xact.hasData()
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val pending_outer_read = io.ignt().hasData()
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val pending_outer_write_ = io.iacq().hasData()
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val pending_outer_read_ = coh.makeGrant(io.iacq(), UInt(trackerId)).hasData()
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io.has_acquire_conflict := xact.conflicts(io.iacq()) &&
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!collect_iacq_data &&
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(state != s_idle)
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io.has_release_match := xact.conflicts(io.irel()) &&
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!io.irel().isVoluntary() &&
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(state != s_idle)
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io.has_acquire_match := Bool(false)
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val outer_write_acq = Bundle(PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = oacq_data_cnt,
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data = data_buffer(oacq_data_cnt)))(outerTLParams)
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val outer_write_rel = Bundle(PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = io.irel().addr_beat,
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data = io.irel().data))(outerTLParams)
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val outer_read = Bundle(GetBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block))(outerTLParams)
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io.outer.acquire.valid := Bool(false)
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io.outer.acquire.bits.payload := outer_read //default
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io.outer.grant.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.probe.bits.header.src := UInt(bankId)
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io.inner.probe.bits.header.dst := curr_p_id
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io.inner.probe.bits.payload := coh.makeProbe(xact)
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits.header.src := UInt(bankId)
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io.inner.grant.bits.header.dst := xact_src
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io.inner.grant.bits.payload := coh.makeGrant(xact, UInt(trackerId)) // Data bypassed in parent
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io.inner.acquire.ready := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.finish.ready := Bool(false)
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when(collect_iacq_data) {
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io.inner.acquire.ready := Bool(true)
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when(io.inner.acquire.valid) {
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data_buffer(io.iacq().addr_beat) := io.iacq().data
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iacq_data_valid(io.iacq().addr_beat) := Bool(true)
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}
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when(iacq_data_done) { collect_iacq_data := Bool(false) }
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}
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when(pending_ognt_ack) {
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io.outer.grant.ready := Bool(true)
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when(io.outer.grant.valid) { pending_ognt_ack := Bool(false) }
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//TODO add finish queue if this isnt the last level manager
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}
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switch (state) {
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is(s_idle) {
|
||
|
|
io.inner.acquire.ready := Bool(true)
|
||
|
|
when(io.inner.acquire.valid) {
|
||
|
|
xact_src := io.inner.acquire.bits.header.src
|
||
|
|
xact := io.iacq()
|
||
|
|
data_buffer(UInt(0)) := io.iacq().data
|
||
|
|
collect_iacq_data := io.iacq().hasMultibeatData()
|
||
|
|
iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat
|
||
|
|
probe_flags := probe_initial_flags
|
||
|
|
release_count := PopCount(probe_initial_flags)
|
||
|
|
state := Mux(probe_initial_flags.orR, s_probe,
|
||
|
|
Mux(pending_outer_write_, s_mem_write,
|
||
|
|
Mux(pending_outer_read_, s_mem_read, s_make_grant)))
|
||
|
|
}
|
||
|
|
}
|
||
|
|
is(s_probe) {
|
||
|
|
// Generate probes
|
||
|
|
io.inner.probe.valid := probe_flags.orR
|
||
|
|
when(io.inner.probe.ready) {
|
||
|
|
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
||
|
|
}
|
||
|
|
|
||
|
|
// Handle releases, which may have data to be written back
|
||
|
|
io.inner.release.ready := !io.irel().hasData() || io.outer.acquire.ready
|
||
|
|
when(io.inner.release.valid) {
|
||
|
|
when(io.irel().hasData()) {
|
||
|
|
io.outer.acquire.valid := Bool(true)
|
||
|
|
io.outer.acquire.bits.payload := outer_write_rel
|
||
|
|
when(io.outer.acquire.ready) {
|
||
|
|
when(oacq_data_done) {
|
||
|
|
pending_ognt_ack := Bool(true)
|
||
|
|
release_count := release_count - UInt(1)
|
||
|
|
when(release_count === UInt(1)) {
|
||
|
|
state := Mux(pending_outer_write, s_mem_write,
|
||
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} .otherwise {
|
||
|
|
release_count := release_count - UInt(1)
|
||
|
|
when(release_count === UInt(1)) {
|
||
|
|
state := Mux(pending_outer_write, s_mem_write,
|
||
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
is(s_mem_write) { // Write data to outer memory
|
||
|
|
io.outer.acquire.valid := !pending_ognt_ack || !collect_iacq_data || iacq_data_valid(oacq_data_cnt)
|
||
|
|
io.outer.acquire.bits.payload := outer_write_acq
|
||
|
|
when(oacq_data_done) {
|
||
|
|
pending_ognt_ack := Bool(true)
|
||
|
|
state := Mux(pending_outer_read, s_mem_read, s_mem_resp)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
is(s_mem_read) { // Read data from outer memory (possibly what was just written)
|
||
|
|
io.outer.acquire.valid := !pending_ognt_ack
|
||
|
|
io.outer.acquire.bits.payload := outer_read
|
||
|
|
when(io.outer.acquire.fire()) { state := s_mem_resp }
|
||
|
|
}
|
||
|
|
is(s_mem_resp) { // Wait to forward grants from outer memory
|
||
|
|
io.outer.grant.ready := io.inner.grant.ready
|
||
|
|
io.inner.grant.valid := io.outer.grant.valid
|
||
|
|
when(ignt_data_done) {
|
||
|
|
state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
is(s_make_grant) { // Manufacture a local grant (some kind of permission upgrade)
|
||
|
|
io.inner.grant.valid := Bool(true)
|
||
|
|
when(io.inner.grant.ready) {
|
||
|
|
state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
is(s_ack) { // Wait for transaction to complete
|
||
|
|
io.inner.finish.ready := Bool(true)
|
||
|
|
when(io.inner.finish.valid) { state := s_idle }
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|