89 lines
3.1 KiB
Scala
89 lines
3.1 KiB
Scala
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// See LICENSE for license details.
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package junctions
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import Chisel._
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object GrayCounter {
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def apply(bits: Int, increment: Bool = Bool(true)): UInt = {
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val binary = RegInit(UInt(0, width = bits))
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val incremented = binary + increment.asUInt()
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binary := incremented
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incremented ^ (incremented >> UInt(1))
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}
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}
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object AsyncGrayCounter {
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def apply(in: UInt, sync: Int): UInt = {
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val syncv = RegInit(Vec.fill(sync){UInt(0, width = in.getWidth)})
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syncv.last := in
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(syncv.init zip syncv.tail).foreach { case (sink, source) => sink := source }
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syncv(0)
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}
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}
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class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the source domain
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val enq = Decoupled(gen).flip()
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// These cross to the sink clock domain
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val ridx = UInt(INPUT, width = bits+1)
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val widx = UInt(OUTPUT, width = bits+1)
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val mem = Vec(depth, gen).asOutput
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}
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val mem = Reg(Vec(depth, gen))
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val widx = GrayCounter(bits+1, io.enq.fire())
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val ridx = AsyncGrayCounter(io.ridx, sync)
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val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
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val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
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when (io.enq.fire() && !reset) { mem(index) := io.enq.bits }
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io.enq.ready := RegNext(ready, Bool(false))
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io.widx := RegNext(widx, UInt(0))
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io.mem := mem
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}
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class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the sink domain
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val deq = Decoupled(gen)
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// These cross to the source clock domain
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val ridx = UInt(OUTPUT, width = bits+1)
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val widx = UInt(INPUT, width = bits+1)
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val mem = Vec(depth, gen).asInput
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}
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val ridx = GrayCounter(bits+1, io.deq.fire())
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val widx = AsyncGrayCounter(io.widx, sync)
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val valid = ridx =/= widx
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// The mux is safe because timing analysis ensures ridx has reached the register
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// On an ASIC, changes to the unread location cannot affect the selected value
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// On an FPGA, only one input changes at a time => mem updates don't cause glitches
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// The register only latches when the selected valued is not being written
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val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
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io.deq.bits := RegEnable(io.mem(index), valid && !reset)
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io.deq.valid := RegNext(valid, Bool(false))
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io.ridx := RegNext(ridx, UInt(0))
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}
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class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] {
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require (sync >= 2)
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require (depth > 0 && isPow2(depth))
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val io = new CrossingIO(gen)
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val source = Module(new AsyncQueueSource(gen, depth, sync, io.enq_clock, io.enq_reset))
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val sink = Module(new AsyncQueueSink (gen, depth, sync, io.deq_clock, io.deq_reset))
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source.io.enq <> io.enq
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io.deq <> sink.io.deq
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sink.io.mem := source.io.mem
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sink.io.widx := source.io.widx
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source.io.ridx := sink.io.ridx
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}
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