riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
d5d076200e
rocket-chip/vsrc/jtag_vpi.tab

2 lines
91 B
Plaintext
Raw Normal View History

Add JTAG DTM and test support in simulation Initial cut checkpoint which compiles and runs but there is some off-by-1 in the protocol Debugging the clock crossing logic checkpoint which works Clean up the AsyncMailbox black box
2016-08-19 18:46:43 +02:00
$send_result_to_server call=send_result_to_server
$check_for_command call=check_for_command
Copy Permalink