61 lines
1.9 KiB
Scala
61 lines
1.9 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.coreplex
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class FrontBusParams(
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beatBytes: Int,
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blockBytes: Int,
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masterBuffering: BufferParams = BufferParams.default,
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slaveBuffering: BufferParams = BufferParams.none // TODO should be BufferParams.none on BCE
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) extends TLBusParams
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case object FrontBusParams extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("FrontBus")
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def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = {
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val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
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for(i<-1 until buffers) {
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buf(i).node :=* buf(i-1).node
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}
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inwardNode :=* buf(buffers-1).node
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if(buffers>0) buf(0).node else inwardNode
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}
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def fromSyncPorts(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = {
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val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
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for(i<-1 until buffers) {
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buf(i).node :=* buf(i-1).node
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}
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inwardNode :=* buf(buffers-1).node
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if(buffers>0) buf(0).node else inwardNode
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}
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def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = fromSyncPorts(params, buffers)
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def toSystemBus : TLOutwardNode = outwardBufNode
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}
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/** Provides buses that serve as attachment points,
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasFrontBus extends HasSystemBus {
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private val frontbusParams = p(FrontBusParams)
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val frontbusBeatBytes = frontbusParams.beatBytes
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val frontbus = new FrontBus(frontbusParams)
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sbus.fromSyncPorts() := frontbus.toSystemBus
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}
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