21 lines
648 B
Scala
21 lines
648 B
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.interrupts
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.util.SynchronizerShiftReg
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import freechips.rocketchip.diplomacy._
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@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
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class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val intnode = IntAdapterNode()
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lazy val module = new LazyModuleImp(this) {
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(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
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out := SynchronizerShiftReg(in, sync)
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}
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}
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}
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