32 lines
692 B
Scala
32 lines
692 B
Scala
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import coreplex._
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trait RocketPlexMaster extends TopNetwork {
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val module: RocketPlexMasterModule
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val mem: Seq[TLInwardNode]
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val coreplex = LazyModule(new DefaultCoreplex)
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socBus.node := coreplex.mmio
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coreplex.mmioInt := intBus.intnode
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(mem zip coreplex.mem) foreach { case (m, c) => m := c }
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}
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trait RocketPlexMasterBundle extends TopNetworkBundle {
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val outer: RocketPlexMaster
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}
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trait RocketPlexMasterModule extends TopNetworkModule {
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val outer: RocketPlexMaster
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val io: RocketPlexMasterBundle
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}
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