36 lines
1.7 KiB
Scala
36 lines
1.7 KiB
Scala
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// See LICENSE for license details.
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package rocketchip
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import Chisel._
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import cde.{Parameters, Field}
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import coreplex.Coreplex
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import rocketchip._
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/** Example Top with Periphery */
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class ExampleTop(q: Parameters) extends BaseTop(q)
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with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryCoreplexLocalInterrupter
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with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
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override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
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}
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class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
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with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryCoreplexLocalInterrupterBundle
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with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
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with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryCoreplexLocalInterrupterModule
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with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
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/** Example Top with TestRAM */
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class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
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with PeripheryTestRAM {
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override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
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}
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class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
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with PeripheryTestRAMBundle
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class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
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with PeripheryTestRAMModule
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