73 lines
1.9 KiB
Scala
73 lines
1.9 KiB
Scala
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package uncore
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import Chisel._
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import junctions.{NASTIMasterIO, NASTIAddrHashMap, SMIIO}
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class RTC(pcr_MTIME: Int) extends Module {
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val io = new NASTIMasterIO
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private val nCores = params(HTIFNCores)
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private val addrMap = params(NASTIAddrHashMap)
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val addrTable = Vec.tabulate(nCores) { i =>
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UInt(addrMap(s"conf:csr$i").start + pcr_MTIME * 8)
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}
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val rtc = Reg(init=UInt(0,64))
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val rtc_tick = Counter(params(RTCPeriod)).inc()
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val sending_addr = Reg(init = Bool(false))
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val sending_data = Reg(init = Bool(false))
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val send_acked = Reg(init = Vec(nCores, Bool(true)))
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when (rtc_tick) {
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rtc := rtc + UInt(1)
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send_acked := Vec(nCores, Bool(false))
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sending_addr := Bool(true)
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sending_data := Bool(true)
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}
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if (nCores > 1) {
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val (core, addr_send_done) = Counter(io.aw.fire(), nCores)
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val (_, data_send_done) = Counter(io.w.fire(), nCores)
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when (addr_send_done) { sending_addr := Bool(false) }
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when (data_send_done) { sending_data := Bool(false) }
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io.aw.bits.id := core
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io.aw.bits.addr := addrTable(core)
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} else {
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when (io.aw.fire()) { sending_addr := Bool(false) }
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when (io.w.fire()) { sending_addr := Bool(false) }
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io.aw.bits.id := UInt(0)
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io.aw.bits.addr := addrTable(0)
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}
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when (io.b.fire()) { send_acked(io.b.bits.id) := Bool(true) }
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io.aw.valid := sending_addr
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io.aw.bits.size := UInt(3) // 8 bytes
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io.aw.bits.len := UInt(0)
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io.aw.bits.burst := Bits("b01")
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io.aw.bits.lock := Bool(false)
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io.aw.bits.cache := UInt("b0000")
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io.aw.bits.prot := UInt("b000")
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io.aw.bits.qos := UInt("b0000")
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io.aw.bits.region := UInt("b0000")
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io.aw.bits.user := UInt(0)
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io.w.valid := sending_data
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io.w.bits.data := rtc
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io.w.bits.strb := Bits(0x00FF)
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io.w.bits.user := UInt(0)
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io.w.bits.last := Bool(true)
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io.b.ready := Bool(true)
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io.ar.valid := Bool(false)
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io.r.ready := Bool(false)
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assert(!rtc_tick || send_acked.toBits.andR,
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s"Not all clocks were updated for rtc tick")
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}
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