95 lines
3.1 KiB
Scala
95 lines
3.1 KiB
Scala
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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/** Specifies widths of various attachement points in the SoC */
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trait TLBusParams {
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val beatBytes: Int
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val blockBytes: Int
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val masterBuffering: BufferParams
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val slaveBuffering: BufferParams
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def beatBits: Int = beatBytes * 8
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def blockBits: Int = blockBytes * 8
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def blockBeats: Int = blockBytes / beatBytes
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def blockOffset: Int = log2Up(blockBytes)
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}
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abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends TLBusParams {
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val beatBytes = params.beatBytes
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val blockBytes = params.blockBytes
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val masterBuffering = params.masterBuffering
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val slaveBuffering = params.slaveBuffering
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require(blockBytes % beatBytes == 0)
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private val xbar = LazyModule(new TLXbar)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
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private val slave_ww = LazyModule(new TLWidthWidget(beatBytes))
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xbar.node :=* master_buffer.node
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slave_buffer.node :*= xbar.node
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slave_frag.node :*= slave_buffer.node
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slave_ww.node :*= slave_buffer.node
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protected def outwardNode: TLOutwardNode = xbar.node
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protected def outwardBufNode: TLOutwardNode = slave_buffer.node
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protected def outwardFragNode: TLOutwardNode = slave_frag.node
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protected def outwardWWNode: TLOutwardNode = slave_ww.node
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protected def inwardNode: TLInwardNode = xbar.node
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protected def inwardBufNode: TLInwardNode = master_buffer.node
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def bufferFromMasters: TLInwardNode = inwardBufNode
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def bufferToSlaves: TLOutwardNode = outwardBufNode
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def toAsyncSlaves(sync: Int = 3): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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source.node :*= outwardNode
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source.node
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}
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def toRationalSlaves: TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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source.node :*= outwardNode
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source.node
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}
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def toVariableWidthSlaves: TLOutwardNode = outwardFragNode
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def toAsyncVariableWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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source.node :*= outwardFragNode
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source.node
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}
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def toRationalVariableWidthSlaves: TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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source.node :*= outwardFragNode
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source.node
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}
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def toFixedWidthSlaves: TLOutwardNode = outwardWWNode
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def toAsyncFixedWidthSlaves(sync: Int = 3): TLAsyncOutwardNode = {
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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source.node := outwardWWNode
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source.node
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}
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def toRationalFixedWidthSlaves: TLRationalOutwardNode = {
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val source = LazyModule(new TLRationalCrossingSource())
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source.node :*= outwardWWNode
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source.node
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}
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def toFixedWidthPorts: TLOutwardNode = outwardWWNode // TODO, do/don't buffer here; knowing we will after the necessary port conversions
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}
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