80 lines
1.7 KiB
Plaintext
80 lines
1.7 KiB
Plaintext
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Quick and dirty instructions:
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CHECKOUT THE CODE:
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git submodule init
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git submodule update
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cd riscv-gcc-isasim
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git submodule init
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git submodule update
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BUILDING THE TOOLCHAIN:
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To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:
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cd riscv-gcc-isasim
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vi build.sh (Edit INSTALL_PREFIX)
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./build.sh
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To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):
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cd riscv-asmtests-bmarks/riscv-tests/
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make
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cd riscv-asmtests-bmarks/riscv-bmarks/
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make
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BUILDING THE PROJECT:
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To build the C simulator:
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cd emulator
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make dramsim2 (if DRAMSim2 is not installed and in your path)
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make
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To build the VCS simulator:
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cd vlsi/build/vcs-sim-rtl
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make
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in either case, you can run a set of assembly tests or simple benchmarks:
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make run-asm-tests
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make run-vecasm-tests
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make run-vecasm-timer-tests
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make run-bmarks-test
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To build a C simulator that is capable of VCD waveform generation:
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cd emulator
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make emulator-debug
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And to run the assembly tests on the C simulator and generate waveforms:
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make run-asm-tests-debug
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make run-vecasm-tests-debug
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make run-vecasm-timer-tests-debug
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make run-bmarks-test-debug
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UPDATING TO A NEWER VERSION OF CHISEL:
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To grab a newer version of chisel:
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git submodule init
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git submodule update
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cd chisel
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git pull origin master
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Then, to compile it and install it into the rocket repo:
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cd sbt
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sbt package
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cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib
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If you commit a new jar, you must also commit the updated chisel submodule.
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